[Microblaze][PATCH]

timer support
interrupt controller support
flash support
ethernet support
cache support
board information support
env support
booting image support

adding support for Xilinx ML401

board/xilinx/ml401/Makefile

@@ -0,0 +1,65 @@
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+ifneq ($(OBJTREE),$(SRCTREE))
+$(shell mkdir -p $(obj)../common)
+$(shell mkdir -p $(obj)../xilinx_enet)
+endif
+
+INCS		:= -I../common -I../xilinx_enet
+CFLAGS		+= $(INCS)
+HOST_CFLAGS	+= $(INCS)
+
+LIB	= $(obj)lib$(BOARD).a
+
+COBJS	= $(BOARD).o \
+	  ../xilinx_enet/emac_adapter.o  ../xilinx_enet/xemac.o \
+	  ../xilinx_enet/xemac_options.o ../xilinx_enet/xemac_polled.o \
+	  ../xilinx_enet/xemac_intr.o ../xilinx_enet/xemac_g.o \
+	  ../xilinx_enet/xemac_intr_dma.o ../common/xipif_v1_23_b.o \
+	  ../common/xbasic_types.o ../common/xdma_channel.o \
+	  ../common/xdma_channel_sg.o ../common/xpacket_fifo_v1_00_b.o \
+	  ../common/xversion.o \
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(OBJS) $(SOBJS)
+	$(AR) $(ARFLAGS) $@ $^
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################

board/xilinx/ml401/config.mk

@@ -0,0 +1,29 @@
+#
+# (C) Copyright 2004 Atmark Techno, Inc.
+#
+# Yasushi SHOJI <yashi@atmark-techno.com>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+TEXT_BASE = 0x12000000
+
+PLATFORM_CPPFLAGS += -mno-xl-soft-mul
+PLATFORM_CPPFLAGS += -mno-xl-soft-div
+PLATFORM_CPPFLAGS += -mxl-barrel-shift

board/xilinx/ml401/ml401.c

@@ -0,0 +1,49 @@
+/*
+ * (C) Copyright 2007 Michal Simek
+ *
+ * Michal  SIMEK <monstr@monstr.eu>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/* This is a board specific file.  It's OK to include board specific
+ * header files */
+
+#include <common.h>
+#include <configs/ml401.h>
+
+void do_reset (void)
+{
+#ifdef CFG_GPIO_0
+	*((unsigned long *)(CFG_GPIO_0_ADDR)) =
+	    ++(*((unsigned long *)(CFG_GPIO_0_ADDR)));
+#endif
+#ifdef CFG_RESET_ADDRESS
+	puts ("Reseting board\n");
+	asm ("bra r0");
+#endif
+}
+
+int gpio_init (void)
+{
+#ifdef CFG_GPIO_0
+	*((unsigned long *)(CFG_GPIO_0_ADDR)) = 0x0;
+#endif
+	return 0;
+}

board/xilinx/ml401/u-boot.lds

@@ -0,0 +1,66 @@
+/*
+ * (C) Copyright 2004 Atmark Techno, Inc.
+ *
+ * Yasushi SHOJI <yashi@atmark-techno.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(microblaze)
+ENTRY(_start)
+
+SECTIONS
+{
+	.text ALIGN(0x4):
+	{
+		__text_start = .;
+		cpu/microblaze/start.o (.text)
+		*(.text)
+		__text_end = .;
+	}
+
+	.rodata ALIGN(0x4):
+	{
+		__rodata_start = .;
+		*(.rodata)
+		__rodata_end = .;
+	}
+
+	.data ALIGN(0x4):
+	{
+		__data_start = .;
+		*(.data)
+		__data_end = .;
+	}
+
+	.u_boot_cmd ALIGN(0x4):
+	{
+		. = .;
+		__u_boot_cmd_start = .;
+		*(.u_boot_cmd)
+		__u_boot_cmd_end = .;
+	}
+
+	.bss ALIGN(0x4):
+	{
+		__bss_start = .;
+		*(.bss)
+		__bss_end = .;
+	}
+}

board/xilinx/ml401/xparameters.h

@@ -0,0 +1,56 @@
+/*
+ * (C) Copyright 2007 Michal Simek
+ *
+ * Michal  SIMEK <monstr@monstr.eu>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/* DDR SDRAM */
+#define CONFIG_XILINX_ERAM_START 0x10000000
+#define CONFIG_XILINX_ERAM_SIZE 0x04000000
+
+/* FLASH_MEMORY Settings */
+#define CONFIG_XILINX_FLASH_START 0x28000000
+#define CONFIG_XILINX_FLASH_SIZE 0x00800000
+
+/* serial line */
+#define CONFIG_XILINX_UARTLITE_0_BASEADDR 0xA0000000
+#define CONFIG_XILINX_UARTLITE_0_BAUDRATE 115200
+
+/* GPIO */
+#define CONFIG_XILINX_GPIO_0_BASEADDR 0x90000000
+
+/* INTC */
+#define CONFIG_XILINX_INTC_0_BASEADDR 0xD1000FC0
+#define CONFIG_XILINX_INTC_0_NUM_INTR_INPUTS 12
+
+/* TIMER */
+#define CONFIG_XILINX_TIMER_0_BASEADDR 0xA2000000
+#define CONFIG_XILINX_TIMER_0_IRQ 0
+
+/* ethernet */
+#define XPAR_XEMAC_NUM_INSTANCES 1
+#define XPAR_OPB_ETHERNET_0_BASEADDR 0x60000000
+#define XPAR_OPB_ETHERNET_0_HIGHADDR 0x60003FFF
+#define XPAR_OPB_ETHERNET_0_DEVICE_ID 0
+#define XPAR_EMAC_0_DEVICE_ID 0
+#define XPAR_OPB_ETHERNET_0_ERR_COUNT_EXIST 1
+#define XPAR_OPB_ETHERNET_0_DMA_PRESENT 1
+#define XPAR_OPB_ETHERNET_0_MII_EXIST 1

cpu/microblaze/cache.c

@@ -0,0 +1,48 @@
+/*
+ * (C) Copyright 2007 Michal Simek
+ *
+ * Michal SIMEK <moonstr@monstr.eu>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+
+#if (CONFIG_COMMANDS & CFG_CMD_CACHE)
+
+int dcache_status (void)
+{
+	int i = 0;
+	int mask = 0x80;
+	__asm__ __volatile__ ("mfs %0,rmsr"::"r" (i):"memory");
+	/* i&=0x80 */
+	__asm__ __volatile__ ("and %0,%0,%1"::"r" (i), "r" (mask):"memory");
+	return i;
+}
+
+int icache_status (void)
+{
+	int i = 0;
+	int mask = 0x20;
+	__asm__ __volatile__ ("mfs %0,rmsr"::"r" (i):"memory");
+	/* i&=0x20 */
+	__asm__ __volatile__ ("and %0,%0,%1"::"r" (i), "r" (mask):"memory");
+	return i;
+}
+#endif

cpu/microblaze/dcache.S

@@ -0,0 +1,68 @@
+/*
+ * (C) Copyright 2007 Michal Simek
+ *
+ * Michal  SIMEK <monstr@monstr.eu>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+	.text
+	.globl	dcache_enable
+	.ent	dcache_enable
+	.align	2
+dcache_enable:
+	/* Make space on stack for a temporary */
+	addi	r1, r1, -4
+	/* Save register r12 */
+	swi	r12, r1, 0
+	/* Read the MSR register */
+	mfs	r12, rmsr
+	/* Set the instruction enable bit */
+	ori	r12, r12, 0x80
+	/* Save the MSR register */
+	mts	rmsr, r12
+	/* Load register r12 */
+	lwi	r12, r1, 0
+	/* Return */
+	rtsd	r15, 8
+	/* Update stack in the delay slot */
+	addi	r1, r1, 4
+	.end	dcache_enable
+
+	.text
+	.globl	dcache_disable
+	.ent	dcache_disable
+	.align	2
+dcache_disable:
+	/* Make space on stack for a temporary */
+	addi	r1, r1, -4
+	/* Save register r12 */
+	swi	r12, r1, 0
+	/* Read the MSR register */
+	mfs	r12, rmsr
+	/* Clear the data cache enable bit */
+	andi	r12, r12, ~0x80
+	/* Save the MSR register */
+	mts	rmsr, r12
+	/* Load register r12 */
+	lwi	r12, r1, 0
+	/* Return */
+	rtsd	r15, 8
+	/* Update stack in the delay slot */
+	addi	r1, r1, 4
+	.end	dcache_disable

cpu/microblaze/disable_int.S

@@ -0,0 +1,46 @@
+/*
+ * (C) Copyright 2007 Michal Simek
+ *
+ * Michal  SIMEK <monstr@monstr.eu>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+	.text
+	.globl	microblaze_disable_interrupts
+	.ent	microblaze_disable_interrupts
+	.align	2
+microblaze_disable_interrupts:
+	#Make space on stack for a temporary
+	addi	r1, r1, -4
+	#Save register r12
+	swi	r12, r1, 0
+	#Read the MSR register
+	mfs	r12, rmsr
+	#Clear the interrupt enable bit
+	andi	r12, r12, ~2
+	#Save the MSR register
+	mts	rmsr, r12
+	#Load register r12
+	lwi	r12, r1, 0
+	#Return
+	rtsd	r15, 8
+	#Update stack in the delay slot
+	addi	r1, r1, 4
+	.end	microblaze_disable_interrupts

cpu/microblaze/enable_int.S

@@ -0,0 +1,38 @@
+/*
+ * (C) Copyright 2007 Michal Simek
+ *
+ * Michal  SIMEK <monstrmonstr.eu>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+	.text
+	.globl	microblaze_enable_interrupts
+	.ent	microblaze_enable_interrupts
+	.align	2
+microblaze_enable_interrupts:
+	addi	r1, r1, -4
+	swi	r12, r1, 0
+	mfs	r12, rmsr
+	ori	r12, r12, 2
+	mts	rmsr, r12
+	lwi	r12, r1, 0
+	rtsd	r15, 8
+	addi	r1, r1, 4
+	.end	microblaze_enable_interrupts

cpu/microblaze/exception.c

@@ -0,0 +1,68 @@
+/*
+ * (C) Copyright 2007 Michal Simek
+ *
+ * Michal  SIMEK <monstr@monstr.eu>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+
+void _hw_exception_handler (void)
+{
+	int address = 0;
+	int state = 0;
+	/* loading address of exception EAR */
+	__asm__ __volatile ("mfs %0,rear"::"r" (address):"memory");
+	/* loading excetpion state register ESR */
+	__asm__ __volatile ("mfs %0,resr"::"r" (state):"memory");
+	printf ("Hardware exception at 0x%x address\n", address);
+	switch (state & 0x1f) {	/* mask on exception cause */
+	case 0x1:
+		puts ("Unaligned data access exception\n");
+		break;
+	case 0x2:
+		puts ("Illegal op-code exception\n");
+		break;
+	case 0x3:
+		puts ("Instruction bus error exception\n");
+		break;
+	case 0x4:
+		puts ("Data bus error exception\n");
+		break;
+	case 0x5:
+		puts ("Divide by zero exception\n");
+		break;
+	default:
+		puts ("Undefined cause\n");
+		break;
+	}
+	printf ("Unaligned %sword access\n", ((state & 0x800) ? "" : "half"));
+	printf ("Unaligned %s access\n", ((state & 0x400) ? "store" : "load"));
+	printf ("Register R%x\n", (state & 0x3E) >> 5);
+	hang ();
+}
+
+#ifdef CFG_USR_EXCEP
+void _exception_handler (void)
+{
+	puts ("User vector_exception\n");
+	hang ();
+}
+#endif

cpu/microblaze/icache.S

@@ -0,0 +1,69 @@
+/*
+ * (C) Copyright 2007 Michal Simek
+ *
+ * Michal  SIMEK <monstr@monstr.eu>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+	.text
+	.globl	icache_enable
+	.ent	icache_enable
+	.align	2
+icache_enable:
+	/* Make space on stack for a temporary */
+	addi	r1, r1, -4
+	/* Save register r12 */
+	swi	r12, r1, 0
+	/* Read the MSR register */
+	mfs	r12, rmsr
+	/* Set the instruction enable bit */
+	ori	r12, r12, 0x20
+	/* Save the MSR register */
+	mts	rmsr, r12
+	/* Load register r12 */
+	lwi	r12, r1, 0
+	/* Return */
+	rtsd	r15, 8
+	/* Update stack in the delay slot */
+	addi	r1, r1, 4
+	.end	icache_enable
+
+	.text
+	.globl	icache_disable
+	.ent	icache_disable
+	.align	2
+icache_disable:
+	/* Make space on stack for a temporary */
+	addi	r1, r1, -4
+	/* Save register r12 */
+	swi	r12, r1, 0
+	/* Read the MSR register */
+	mfs	r12, rmsr
+	/* Clear the instruction enable bit */
+	andi	r12, r12, ~0x20
+	/* Save the MSR register */
+	mts	rmsr, r12
+	/* Load register r12 */
+	lwi	r12, r1, 0
+	/* Return */
+	rtsd	r15, 8
+	/* Update stack in the delay slot */
+	addi	r1, r1, 4
+	.end	icache_disable

cpu/microblaze/irq.S

@@ -0,0 +1,165 @@
+/*
+ * (C) Copyright 2007 Michal Simek
+ *
+ * Michal  SIMEK <monstr@monstr.eu>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+	.text
+	.global _interrupt_handler
+_interrupt_handler:
+	addi	r1, r1, -4
+	swi	r2, r1, 0
+	addi	r1, r1, -4
+	swi	r3, r1, 0
+	addi	r1, r1, -4
+	swi	r4, r1, 0
+	addi	r1, r1, -4
+	swi	r5, r1, 0
+	addi	r1, r1, -4
+	swi	r6, r1, 0
+	addi	r1, r1, -4
+	swi	r7, r1, 0
+	addi	r1, r1, -4
+	swi	r8, r1, 0
+	addi	r1, r1, -4
+	swi	r9, r1, 0
+	addi	r1, r1, -4
+	swi	r10, r1, 0
+	addi	r1, r1, -4
+	swi	r11, r1, 0
+	addi	r1, r1, -4
+	swi	r12, r1, 0
+	addi	r1, r1, -4
+	swi	r13, r1, 0
+	addi	r1, r1, -4
+	swi	r14, r1, 0
+	addi	r1, r1, -4
+	swi	r15, r1, 0
+	addi	r1, r1, -4
+	swi	r16, r1, 0
+	addi	r1, r1, -4
+	swi	r17, r1, 0
+	addi	r1, r1, -4
+	swi	r18, r1, 0
+	addi	r1, r1, -4
+	swi	r19, r1, 0
+	addi	r1, r1, -4
+	swi	r20, r1, 0
+	addi	r1, r1, -4
+	swi	r21, r1, 0
+	addi	r1, r1, -4
+	swi	r22, r1, 0
+	addi	r1, r1, -4
+	swi	r23, r1, 0
+	addi	r1, r1, -4
+	swi	r24, r1, 0
+	addi	r1, r1, -4
+	swi	r25, r1, 0
+	addi	r1, r1, -4
+	swi	r26, r1, 0
+	addi	r1, r1, -4
+	swi	r27, r1, 0
+	addi	r1, r1, -4
+	swi	r28, r1, 0
+	addi	r1, r1, -4
+	swi	r29, r1, 0
+	addi	r1, r1, -4
+	swi	r30, r1, 0
+	addi	r1, r1, -4
+	swi	r31, r1, 0
+	brlid	r15, interrupt_handler
+	nop
+	nop
+	lwi	r31, r1, 0
+	addi	r1, r1, 4
+	lwi	r30, r1, 0
+	addi	r1, r1, 4
+	lwi	r29, r1, 0
+	addi	r1, r1, 4
+	lwi	r28, r1, 0
+	addi	r1, r1, 4
+	lwi	r27, r1, 0
+	addi	r1, r1, 4
+	lwi	r26, r1, 0
+	addi	r1, r1, 4
+	lwi	r25, r1, 0
+	addi	r1, r1, 4
+	lwi	r24, r1, 0
+	addi	r1, r1, 4
+	lwi	r23, r1, 0
+	addi	r1, r1, 4
+	lwi	r22, r1, 0
+	addi	r1, r1, 4
+	lwi	r21, r1, 0
+	addi	r1, r1, 4
+	lwi	r20, r1, 0
+	addi	r1, r1, 4
+	lwi	r19, r1, 0
+	addi	r1, r1, 4
+	lwi	r18, r1, 0
+	addi	r1, r1, 4
+	lwi	r17, r1, 0
+	addi	r1, r1, 4
+	lwi	r16, r1, 0
+	addi	r1, r1, 4
+	lwi	r15, r1, 0
+	addi	r1, r1, 4
+	lwi	r14, r1, 0
+	addi	r1, r1, 4
+	lwi	r13, r1, 0
+	addi	r1, r1, 4
+	lwi	r12, r1, 0
+	addi	r1, r1, 4
+	lwi	r11, r1, 0
+	addi	r1, r1, 4
+	lwi	r10, r1, 0
+	addi	r1, r1, 4
+	lwi	r9, r1, 0
+	addi	r1, r1, 4
+	lwi	r8, r1, 0
+	addi	r1, r1, 4
+	lwi	r7, r1, 0
+	addi	r1, r1, 4
+	lwi	r6, r1, 0
+	addi	r1, r1, 4
+	lwi	r5, r1, 0
+	addi	r1, r1, 4
+	lwi	r4, r1, 0
+	addi	r1, r1, 4
+	lwi	r3, r1, 0
+	addi	r1, r1, 4
+	lwi	r2, r1, 0
+	addi	r1, r1, 4
+
+	/* enable_interrupt */
+	addi	r1, r1, -4
+	swi	r12, r1, 0
+	mfs	r12, rmsr
+	ori	r12, r12, 2
+	mts	rmsr, r12
+	lwi	r12, r1, 0
+	addi	r1, r1, 4
+	nop
+	bra	r14
+	nop
+	nop
+	.size _interrupt_handler,.-_interrupt_handler

cpu/microblaze/timer.c

@@ -0,0 +1,68 @@
+/*
+ * (C) Copyright 2007 Michal Simek
+ *
+ * Michal  SIMEK <monstr@monstr.eu>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/microblaze_timer.h>
+
+volatile int timestamp = 0;
+
+void reset_timer (void)
+{
+	timestamp = 0;
+}
+
+ulong get_timer (ulong base)
+{
+	return (timestamp - base);
+}
+
+void set_timer (ulong t)
+{
+	timestamp = t;
+}
+
+#ifdef CFG_INTC_0
+#ifdef CFG_TIMER_0
+extern void install_interrupt_handler (int irq, interrupt_handler_t * hdlr,
+				       void *arg);
+
+microblaze_timer_t *tmr = (microblaze_timer_t *) (CFG_TIMER_0_ADDR);
+
+void timer_isr (void *arg)
+{
+	timestamp++;
+	tmr->control = tmr->control | TIMER_INTERRUPT;
+}
+
+void timer_init (void)
+{
+	tmr->loadreg = CFG_TIMER_0_PRELOAD;
+	tmr->control = TIMER_INTERRUPT | TIMER_RESET;
+	tmr->control =
+	    TIMER_ENABLE | TIMER_ENABLE_INTR | TIMER_RELOAD | TIMER_DOWN_COUNT;
+	reset_timer ();
+	install_interrupt_handler (CFG_TIMER_0_IRQ, timer_isr, (void *)tmr);
+}
+#endif
+#endif

include/asm-microblaze/microblaze_intc.h

@@ -0,0 +1,41 @@
+/*
+ * (C) Copyright 2007 Michal Simek
+ *
+ * Michal  SIMEK <monstr@monstr.cz>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+typedef volatile struct microblaze_intc_t {
+	int isr; /* interrupt status register */
+	int ipr; /* interrupt pending register */
+	int ier; /* interrupt enable register */
+	int iar; /* interrupt acknowledge register */
+	int sie; /* set interrupt enable bits */
+	int cie; /* clear interrupt enable bits */
+	int ivr; /* interrupt vector register */
+	int mer; /* master enable register */
+} microblaze_intc_t;
+
+struct irq_action {
+	interrupt_handler_t *handler; /* pointer to interrupt rutine */
+	void *arg;
+	int count; /* number of interrupt */
+};
+

include/asm-microblaze/microblaze_timer.h

@@ -0,0 +1,42 @@
+/*
+ * (C) Copyright 2007 Michal Simek
+ *
+ * Michal  SIMEK <monstr@monstr.cz>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#define TIMER_ENABLE_ALL    0x400 /* ENALL */
+#define TIMER_PWM           0x200 /* PWMA0 */
+#define TIMER_INTERRUPT     0x100 /* T0INT */
+#define TIMER_ENABLE        0x080 /* ENT0 */
+#define TIMER_ENABLE_INTR   0x040 /* ENIT0 */
+#define TIMER_RESET         0x020 /* LOAD0 */
+#define TIMER_RELOAD        0x010 /* ARHT0 */
+#define TIMER_EXT_CAPTURE   0x008 /* CAPT0 */
+#define TIMER_EXT_COMPARE   0x004 /* GENT0 */
+#define TIMER_DOWN_COUNT    0x002 /* UDT0 */
+#define TIMER_CAPTURE_MODE  0x001 /* MDT0 */
+
+typedef volatile struct microblaze_timer_t {
+	int control; /* control/statuc register TCSR */
+	int loadreg; /* load register TLR */
+	int counter; /* timer/counter register */
+} microblaze_timer_t;
+

include/configs/ml401.h

@@ -0,0 +1,221 @@
+/*
+ * (C) Copyright 2007 Czech Technical University.
+ *
+ * Michal SIMEK <monstr@seznam.cz>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include "../board/xilinx/ml401/xparameters.h"
+
+#define	CONFIG_MICROBLAZE	1	/* MicroBlaze CPU */
+#define	CONFIG_ML401		1	/* ML401 Board */
+
+/* uart */
+#define	CONFIG_SERIAL_BASE	CONFIG_XILINX_UARTLITE_0_BASEADDR
+#define	CONFIG_BAUDRATE		CONFIG_XILINX_UARTLITE_0_BAUDRATE
+#define	CFG_BAUDRATE_TABLE	{ CONFIG_BAUDRATE }
+
+/* setting reset address */
+#define	CFG_RESET_ADDRESS	TEXT_BASE
+
+/* gpio */
+#define	CFG_GPIO_0		1
+#define	CFG_GPIO_0_ADDR		CONFIG_XILINX_GPIO_0_BASEADDR
+
+/* interrupt controller */
+#define	CFG_INTC_0		1
+#define	CFG_INTC_0_ADDR		CONFIG_XILINX_INTC_0_BASEADDR
+#define	CFG_INTC_0_NUM		CONFIG_XILINX_INTC_0_NUM_INTR_INPUTS
+
+/* timer */
+#define	CFG_TIMER_0		1
+#define	CFG_TIMER_0_ADDR	CONFIG_XILINX_TIMER_0_BASEADDR
+#define	CFG_TIMER_0_IRQ		CONFIG_XILINX_TIMER_0_IRQ
+#define	FREQUENCE		66666666
+#define	CFG_TIMER_0_PRELOAD	( FREQUENCE/1000 )
+
+/*
+ * memory layout - Example
+ * TEXT_BASE = 0x1200_0000;
+ * CFG_SRAM_BASE = 0x1000_0000;
+ * CFG_SRAM_SIZE = 0x0400_0000;
+ *
+ * CFG_GBL_DATA_OFFSET = 0x1000_0000 + 0x0400_0000 - 0x1000 = 0x13FF_F000
+ * CFG_MONITOR_BASE = 0x13FF_F000 - 0x40000 = 0x13FB_F000
+ *
+ * 0x1000_0000	CFG_SDRAM_BASE
+ *					FREE
+ * 0x1200_0000	TEXT_BASE
+ *		U-BOOT code
+ * 0x1202_0000
+ *					FREE
+ *
+ *					STACK
+ * 0x11FB_F000	CFG_MONITOR_BASE
+ *					MONITOR_CODE
+ * 0x13FF_F000	CFG_GBL_DATA_OFFSET
+ * 					GLOBAL_DATA
+ * 0x1400_0000	CFG_SDRAM_BASE + CFG_SDRAM_SIZE
+ */
+
+/* ddr sdram - main memory */
+#define	CFG_SDRAM_BASE		CONFIG_XILINX_ERAM_START
+#define	CFG_SDRAM_SIZE		CONFIG_XILINX_ERAM_SIZE
+#define	CFG_MEMTEST_START	CFG_SDRAM_BASE
+#define	CFG_MEMTEST_END		(CFG_SDRAM_BASE + 0x1000)
+
+/* global pointer */
+#define	CFG_GBL_DATA_SIZE	0x1000	/* size of global data */
+#define	CFG_GBL_DATA_OFFSET     (CFG_SDRAM_BASE + CFG_SDRAM_SIZE - CFG_GBL_DATA_SIZE) /* start of global data */
+
+/* monitor code */
+#define	SIZE			0x40000
+#define	CFG_MONITOR_LEN		SIZE
+#define	CFG_MONITOR_BASE	(CFG_GBL_DATA_OFFSET - CFG_MONITOR_LEN)
+#define	CFG_MALLOC_LEN		SIZE
+
+/* stack */
+#define	CFG_INIT_SP_OFFSET	CFG_MONITOR_BASE
+
+/*#define	RAMENV */
+#define	FLASH
+
+#ifdef FLASH
+	#define	CFG_FLASH_BASE		CONFIG_XILINX_FLASH_START
+	#define	CFG_FLASH_SIZE		CONFIG_XILINX_FLASH_SIZE
+	#define	CFG_FLASH_CFI		1
+	#define	CFG_FLASH_CFI_DRIVER	1
+	#define	CFG_FLASH_EMPTY_INFO	1	/* ?empty sector */
+	#define	CFG_MAX_FLASH_BANKS	1	/* max number of memory banks */
+	#define	CFG_MAX_FLASH_SECT	128	/* max number of sectors on one chip */
+
+	#ifdef	RAMENV
+		#define	CFG_ENV_IS_NOWHERE	1
+		#define	CFG_ENV_SIZE		0x1000
+		#define	CFG_ENV_ADDR		(CFG_MONITOR_BASE - CFG_ENV_SIZE)
+
+	#else	/* !RAMENV */
+		#define	CFG_ENV_IS_IN_FLASH	1
+		#define	CFG_ENV_ADDR		0x40000
+		#define	CFG_ENV_SECT_SIZE	0x40000	/* 256K(one sector) for env */
+		#define	CFG_ENV_SIZE		0x2000
+	#endif /* !RAMBOOT */
+#else /* !FLASH */
+	/* ENV in RAM */
+	#define	CFG_NO_FLASH		1
+	#define	CFG_ENV_IS_NOWHERE	1
+	#define	CFG_ENV_SIZE		0x1000
+	#define	CFG_ENV_ADDR		(CFG_MONITOR_BASE - CFG_ENV_SIZE)
+#endif /* !FLASH */
+
+#ifdef	FLASH
+	#ifdef	RAMENV
+	#define	CONFIG_COMMANDS	(CONFIG__CMD_DFL |\
+				CFG_CMD_MEMORY |\
+				CFG_CMD_MISC |\
+				CFG_CMD_AUTOSCRIPT |\
+				CFG_CMD_IRQ |\
+				CFG_CMD_ASKENV |\
+				CFG_CMD_BDI |\
+				CFG_CMD_RUN |\
+				CFG_CMD_LOADS |\
+				CFG_CMD_LOADB |\
+				CFG_CMD_IMI |\
+				CFG_CMD_NET |\
+				CFG_CMD_CACHE |\
+				CFG_CMD_IMLS |\
+				CFG_CMD_FLASH |\
+				CFG_CMD_PING \
+				)
+	#else	/* !RAMENV */
+	#define	CONFIG_COMMANDS	(CONFIG__CMD_DFL |\
+				CFG_CMD_MEMORY |\
+				CFG_CMD_MISC |\
+				CFG_CMD_AUTOSCRIPT |\
+				CFG_CMD_IRQ |\
+				CFG_CMD_ASKENV |\
+				CFG_CMD_BDI |\
+				CFG_CMD_RUN |\
+				CFG_CMD_LOADS |\
+				CFG_CMD_LOADB |\
+				CFG_CMD_IMI |\
+				CFG_CMD_NET |\
+				CFG_CMD_CACHE |\
+				CFG_CMD_IMLS |\
+				CFG_CMD_FLASH |\
+				CFG_CMD_PING |\
+				CFG_CMD_ENV |\
+				CFG_CMD_SAVES \
+				)
+
+	#endif
+
+#else	/* !FLASH */
+	#define	CONFIG_COMMANDS	(CONFIG__CMD_DFL |\
+				CFG_CMD_MEMORY |\
+				CFG_CMD_MISC |\
+				CFG_CMD_AUTOSCRIPT |\
+				CFG_CMD_IRQ |\
+				CFG_CMD_ASKENV |\
+				CFG_CMD_BDI |\
+				CFG_CMD_RUN |\
+				CFG_CMD_LOADS |\
+				CFG_CMD_LOADB |\
+				CFG_CMD_IMI |\
+				CFG_CMD_NET |\
+				CFG_CMD_CACHE |\
+				CFG_CMD_PING \
+				)
+#endif	/* !FLASH */
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#include <cmd_confdefs.h>
+
+/* Miscellaneous configurable options */
+#define	CFG_PROMPT	"U-Boot-mONStR> "
+#define	CFG_CBSIZE	512	/* size of console buffer */
+#define	CFG_PBSIZE	(CFG_CBSIZE + sizeof(CFG_PROMPT) + 16) /* print buffer size */
+#define	CFG_MAXARGS	15	/* max number of command args */
+#define	CFG_LONGHELP
+#define	CFG_LOAD_ADDR	0x12000000 /* default load address */
+
+#define	CONFIG_BOOTDELAY 	30
+#define	CONFIG_BOOTARGS		"root=romfs"
+#define	CONFIG_HOSTNAME		"ml401"
+#define	CONFIG_BOOTCOMMAND 	"base 0;tftp 11000000 image.img;bootm"
+#define	CONFIG_IPADDR		192.168.0.3
+#define	CONFIG_SERVERIP 	192.168.0.5
+#define	CONFIG_GATEWAYIP 	192.168.0.1
+#define	CONFIG_ETHADDR		00:E0:0C:00:00:FD
+
+/* architecture dependent code */
+#define	CFG_USR_EXCEP	/* user exception */
+#define CFG_HZ	1000
+
+/* system ace */
+/*#define CONFIG_SYSTEMACE
+#define DEBUG_SYSTEMACE
+#define CFG_SYSTEMACE_BASE 0xCF000000
+#define CFG_SYSTEMACE_WIDTH	8
+#define CONFIG_DOS_PARTITION
+*/
+#endif	/* __CONFIG_H */