PXA: Remove "wepep250" board

This board is broken and impossible to repair without deep knowledge or
availability of the hardware.

Signed-off-by: Marek Vasut <marek.vasut@gmail.com>

board/wepep250/Makefile

@@ -1,51 +0,0 @@
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).a
-
-COBJS	:= wepep250.o flash.o
-SOBJS	:= lowlevel_init.o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
-
-$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
-	$(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
-
-clean:
-	rm -f $(SOBJS) $(OBJS)
-
-distclean:	clean
-	rm -f $(LIB) core *.bak $(obj).depend
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################

board/wepep250/config.mk

@@ -1,11 +0,0 @@
-#
-# This is config used for compilation of WEP EP250 sources
-#
-# You might change location of U-Boot in memory by setting right CONFIG_SYS_TEXT_BASE.
-# This allows for example having one copy located at the end of ram and stored
-# in flash device and later on while developing use other location to test
-# the code in RAM device only.
-#
-
-CONFIG_SYS_TEXT_BASE = 0xa1fe0000
-#CONFIG_SYS_TEXT_BASE = 0xa1001000

board/wepep250/flash.c

@@ -1,324 +0,0 @@
-/*
- * Copyright (C) 2003 ETC s.r.o.
- *
- * This code was inspired by Marius Groeger and Kyle Harris code
- * available in other board ports for U-Boot
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- *
- * Written by Peter Figuli <peposh@etc.sk>, 2003.
- *
- */
-
-#include <common.h>
-#include "intel.h"
-
-
-/*
- * This code should handle CFI FLASH memory device. This code is very
- * minimalistic approach without many essential error handling code as well.
- * Because U-Boot actually is missing smart handling of FLASH device,
- * we just set flash_id to anything else to FLASH_UNKNOW, so common code
- * can call us without any restrictions.
- * TODO: Add CFI Query, to be able to determine FLASH device.
- * TODO: Add error handling code
- * NOTE: This code was tested with BUS_WIDTH 4 and ITERLEAVE 2 only, but
- *       hopefully may work with other configurations.
- */
-
-#if ( WEP_FLASH_BUS_WIDTH == 1 )
-#  define FLASH_BUS vu_char
-#  define FLASH_BUS_RET u_char
-#  if ( WEP_FLASH_INTERLEAVE == 1 )
-#    define FLASH_CMD( x ) x
-#  else
-#    error "With 8bit bus only one chip is allowed"
-#  endif
-
-
-#elif ( WEP_FLASH_BUS_WIDTH == 2 )
-#  define FLASH_BUS vu_short
-#  define FLASH_BUS_RET u_short
-#  if ( WEP_FLASH_INTERLEAVE == 1 )
-#    define FLASH_CMD( x ) x
-#  elif ( WEP_FLASH_INTERLEAVE == 2 )
-#    define FLASH_CMD( x ) (( x << 8 )| x )
-#  else
-#    error "With 16bit bus only 1 or 2 chip(s) are allowed"
-#  endif
-
-
-#elif ( WEP_FLASH_BUS_WIDTH == 4 )
-#  define FLASH_BUS vu_long
-#  define FLASH_BUS_RET u_long
-#  if ( WEP_FLASH_INTERLEAVE == 1 )
-#    define FLASH_CMD( x ) x
-#  elif ( WEP_FLASH_INTERLEAVE == 2 )
-#    define FLASH_CMD( x ) (( x << 16 )| x )
-#  elif ( WEP_FLASH_INTERLEAVE == 4 )
-#    define FLASH_CMD( x ) (( x << 24 )|( x << 16 ) ( x << 8 )| x )
-#  else
-#    error "With 32bit bus only 1,2 or 4 chip(s) are allowed"
-#  endif
-
-#else
-#  error "Flash bus width might be 1,2,4 for 8,16,32 bit configuration"
-#endif
-
-
-flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS];
-
-static FLASH_BUS_RET flash_status_reg (void)
-{
-
-	FLASH_BUS *addr = (FLASH_BUS *) 0;
-
-	*addr = FLASH_CMD (CFI_INTEL_CMD_READ_STATUS_REGISTER);
-
-	return *addr;
-}
-
-static int flash_ready (ulong timeout)
-{
-	int ok = 1;
-
-	reset_timer_masked ();
-	while ((flash_status_reg () & FLASH_CMD (CFI_INTEL_SR_READY)) !=
-		   FLASH_CMD (CFI_INTEL_SR_READY)) {
-		if (get_timer_masked () > timeout && timeout != 0) {
-			ok = 0;
-			break;
-		}
-	}
-	return ok;
-}
-
-#if ( CONFIG_SYS_MAX_FLASH_BANKS != 1 )
-#  error "WEP platform has only one flash bank!"
-#endif
-
-
-ulong flash_init (void)
-{
-	int i;
-	FLASH_BUS address = WEP_FLASH_BASE;
-
-	flash_info[0].size = WEP_FLASH_BANK_SIZE;
-	flash_info[0].sector_count = CONFIG_SYS_MAX_FLASH_SECT;
-	flash_info[0].flash_id = INTEL_MANUFACT;
-	memset (flash_info[0].protect, 0, CONFIG_SYS_MAX_FLASH_SECT);
-
-	for (i = 0; i < CONFIG_SYS_MAX_FLASH_SECT; i++) {
-		flash_info[0].start[i] = address;
-#ifdef WEP_FLASH_UNLOCK
-		/* Some devices are hw locked after start. */
-		*((FLASH_BUS *) address) = FLASH_CMD (CFI_INTEL_CMD_LOCK_SETUP);
-		*((FLASH_BUS *) address) = FLASH_CMD (CFI_INTEL_CMD_UNLOCK_BLOCK);
-		flash_ready (0);
-		*((FLASH_BUS *) address) = FLASH_CMD (CFI_INTEL_CMD_READ_ARRAY);
-#endif
-		address += WEP_FLASH_SECT_SIZE;
-	}
-
-	flash_protect (FLAG_PROTECT_SET,
-				   CONFIG_SYS_FLASH_BASE,
-				   CONFIG_SYS_FLASH_BASE + monitor_flash_len - 1,
-				   &flash_info[0]);
-
-	flash_protect (FLAG_PROTECT_SET,
-				   CONFIG_ENV_ADDR,
-				   CONFIG_ENV_ADDR + CONFIG_ENV_SIZE - 1, &flash_info[0]);
-
-	return WEP_FLASH_BANK_SIZE;
-}
-
-void flash_print_info (flash_info_t * info)
-{
-	int i;
-
-	printf (" Intel vendor\n");
-	printf ("  Size: %ld MB in %d Sectors\n",
-			info->size >> 20, info->sector_count);
-
-	printf ("  Sector Start Addresses:");
-	for (i = 0; i < info->sector_count; i++) {
-		if (!(i % 5)) {
-			printf ("\n");
-		}
-
-		printf (" %08lX%s", info->start[i],
-				info->protect[i] ? " (RO)" : "     ");
-	}
-	printf ("\n");
-}
-
-
-int flash_erase (flash_info_t * info, int s_first, int s_last)
-{
-	int flag, non_protected = 0, sector;
-	int rc = ERR_OK;
-
-	FLASH_BUS *address;
-
-	for (sector = s_first; sector <= s_last; sector++) {
-		if (!info->protect[sector]) {
-			non_protected++;
-		}
-	}
-
-	if (!non_protected) {
-		return ERR_PROTECTED;
-	}
-
-	/*
-	 * Disable interrupts which might cause a timeout
-	 * here. Remember that our exception vectors are
-	 * at address 0 in the flash, and we don't want a
-	 * (ticker) exception to happen while the flash
-	 * chip is in programming mode.
-	 */
-	flag = disable_interrupts ();
-
-
-	/* Start erase on unprotected sectors */
-	for (sector = s_first; sector <= s_last && !ctrlc (); sector++) {
-		if (info->protect[sector]) {
-			printf ("Protected sector %2d skipping...\n", sector);
-			continue;
-		} else {
-			printf ("Erasing sector %2d ... ", sector);
-		}
-
-		address = (FLASH_BUS *) (info->start[sector]);
-
-		*address = FLASH_CMD (CFI_INTEL_CMD_BLOCK_ERASE);
-		*address = FLASH_CMD (CFI_INTEL_CMD_CONFIRM);
-		if (flash_ready (CONFIG_SYS_FLASH_ERASE_TOUT)) {
-			*address = FLASH_CMD (CFI_INTEL_CMD_CLEAR_STATUS_REGISTER);
-			printf ("ok.\n");
-		} else {
-			*address = FLASH_CMD (CFI_INTEL_CMD_SUSPEND);
-			rc = ERR_TIMOUT;
-			printf ("timeout! Aborting...\n");
-			break;
-		}
-		*address = FLASH_CMD (CFI_INTEL_CMD_READ_ARRAY);
-	}
-	if (ctrlc ())
-		printf ("User Interrupt!\n");
-
-	/* allow flash to settle - wait 10 ms */
-	udelay_masked (10000);
-	if (flag) {
-		enable_interrupts ();
-	}
-
-	return rc;
-}
-
-static int write_data (flash_info_t * info, ulong dest, FLASH_BUS data)
-{
-	FLASH_BUS *address = (FLASH_BUS *) dest;
-	int rc = ERR_OK;
-	int flag;
-
-	/* Check if Flash is (sufficiently) erased */
-	if ((*address & data) != data) {
-		return ERR_NOT_ERASED;
-	}
-
-	/*
-	 * Disable interrupts which might cause a timeout
-	 * here. Remember that our exception vectors are
-	 * at address 0 in the flash, and we don't want a
-	 * (ticker) exception to happen while the flash
-	 * chip is in programming mode.
-	 */
-
-	flag = disable_interrupts ();
-
-	*address = FLASH_CMD (CFI_INTEL_CMD_CLEAR_STATUS_REGISTER);
-	*address = FLASH_CMD (CFI_INTEL_CMD_PROGRAM1);
-	*address = data;
-
-	if (!flash_ready (CONFIG_SYS_FLASH_WRITE_TOUT)) {
-		*address = FLASH_CMD (CFI_INTEL_CMD_SUSPEND);
-		rc = ERR_TIMOUT;
-		printf ("timeout! Aborting...\n");
-	}
-
-	*address = FLASH_CMD (CFI_INTEL_CMD_READ_ARRAY);
-	if (flag) {
-		enable_interrupts ();
-	}
-
-	return rc;
-}
-
-int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
-{
-	ulong read_addr, write_addr;
-	FLASH_BUS data;
-	int i, result = ERR_OK;
-
-
-	read_addr = addr & ~(sizeof (FLASH_BUS) - 1);
-	write_addr = read_addr;
-	if (read_addr != addr) {
-		data = 0;
-		for (i = 0; i < sizeof (FLASH_BUS); i++) {
-			if (read_addr < addr || cnt == 0) {
-				data |= *((uchar *) read_addr) << i * 8;
-			} else {
-				data |= (*src++) << i * 8;
-				cnt--;
-			}
-			read_addr++;
-		}
-		if ((result = write_data (info, write_addr, data)) != ERR_OK) {
-			return result;
-		}
-		write_addr += sizeof (FLASH_BUS);
-	}
-	for (; cnt >= sizeof (FLASH_BUS); cnt -= sizeof (FLASH_BUS)) {
-		if ((result = write_data (info, write_addr,
-								  *((FLASH_BUS *) src))) != ERR_OK) {
-			return result;
-		}
-		write_addr += sizeof (FLASH_BUS);
-		src += sizeof (FLASH_BUS);
-	}
-	if (cnt > 0) {
-		read_addr = write_addr;
-		data = 0;
-		for (i = 0; i < sizeof (FLASH_BUS); i++) {
-			if (cnt > 0) {
-				data |= (*src++) << i * 8;
-				cnt--;
-			} else {
-				data |= *((uchar *) read_addr) << i * 8;
-			}
-			read_addr++;
-		}
-		if ((result = write_data (info, write_addr, data)) != 0) {
-			return result;
-		}
-	}
-	return ERR_OK;
-}

board/wepep250/intel.h

@@ -1,99 +0,0 @@
-/*
- * Copyright (C) 2002 ETC s.r.o.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the distribution.
- * 3. Neither the name of the ETC s.r.o. nor the names of its contributors
- *    may be used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * Written by Marcel Telka <marcel@telka.sk>, 2002.
- *
- * Documentation:
- * [1] Intel Corporation, "3 Volt Intel Strata Flash Memory 28F128J3A, 28F640J3A,
- *     28F320J3A (x8/x16)", April 2002, Order Number: 290667-011
- * [2] Intel Corporation, "3 Volt Synchronous Intel Strata Flash Memory 28F640K3, 28F640K18,
- *     28F128K3, 28F128K18, 28F256K3, 28F256K18 (x16)", June 2002, Order Number: 290737-005
- *
- * This file is taken from OpenWinCE project hosted by SourceForge.net
- *
- */
-
-#ifndef	FLASH_INTEL_H
-#define	FLASH_INTEL_H
-
-#include <common.h>
-
-/* Intel CFI commands - see Table 4. in [1] and Table 3. in [2] */
-
-#define	CFI_INTEL_CMD_READ_ARRAY		0xFF	/* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
-#define	CFI_INTEL_CMD_READ_IDENTIFIER		0x90	/* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
-#define	CFI_INTEL_CMD_READ_QUERY		0x98	/* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
-#define	CFI_INTEL_CMD_READ_STATUS_REGISTER	0x70	/* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
-#define	CFI_INTEL_CMD_CLEAR_STATUS_REGISTER	0x50	/* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
-#define	CFI_INTEL_CMD_PROGRAM1			0x40	/* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
-#define	CFI_INTEL_CMD_PROGRAM2			0x10	/* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
-#define	CFI_INTEL_CMD_WRITE_TO_BUFFER		0xE8	/* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
-#define	CFI_INTEL_CMD_CONFIRM			0xD0	/* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
-#define	CFI_INTEL_CMD_BLOCK_ERASE		0x20	/* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
-#define	CFI_INTEL_CMD_SUSPEND			0xB0	/* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
-#define	CFI_INTEL_CMD_RESUME			0xD0	/* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
-#define	CFI_INTEL_CMD_LOCK_SETUP		0x60	/* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
-#define	CFI_INTEL_CMD_LOCK_BLOCK		0x01	/* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
-#define	CFI_INTEL_CMD_UNLOCK_BLOCK		0xD0	/* 28FxxxJ3A - unlocks all blocks, 28FFxxxK3, 28FxxxK18 */
-#define	CFI_INTEL_CMD_LOCK_DOWN_BLOCK		0x2F	/* 28FxxxK3, 28FxxxK18 */
-
-/* Intel CFI Status Register bits - see Table 6. in [1] and Table 7. in [2] */
-
-#define	CFI_INTEL_SR_READY			1 << 7	/* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
-#define	CFI_INTEL_SR_ERASE_SUSPEND		1 << 6	/* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
-#define	CFI_INTEL_SR_ERASE_ERROR		1 << 5	/* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
-#define	CFI_INTEL_SR_PROGRAM_ERROR		1 << 4	/* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
-#define	CFI_INTEL_SR_VPEN_ERROR			1 << 3	/* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
-#define	CFI_INTEL_SR_PROGRAM_SUSPEND		1 << 2	/* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
-#define	CFI_INTEL_SR_BLOCK_LOCKED		1 << 1	/* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
-#define	CFI_INTEL_SR_BEFP			1 << 0	/* 28FxxxK3, 28FxxxK18 */
-
-/* Intel flash device ID codes for 28FxxxJ3A - see Table 5. in [1] */
-
-#define	CFI_CHIP_INTEL_28F320J3A		0x0016
-#define	CFI_CHIPN_INTEL_28F320J3A		"28F320J3A"
-#define	CFI_CHIP_INTEL_28F640J3A		0x0017
-#define	CFI_CHIPN_INTEL_28F640J3A		"28F640J3A"
-#define	CFI_CHIP_INTEL_28F128J3A		0x0018
-#define	CFI_CHIPN_INTEL_28F128J3A		"28F128J3A"
-
-/* Intel flash device ID codes for 28FxxxK3 and 28FxxxK18 - see Table 8. in [2] */
-
-#define	CFI_CHIP_INTEL_28F640K3			0x8801
-#define	CFI_CHIPN_INTEL_28F640K3		"28F640K3"
-#define	CFI_CHIP_INTEL_28F128K3			0x8802
-#define	CFI_CHIPN_INTEL_28F128K3		"28F128K3"
-#define	CFI_CHIP_INTEL_28F256K3			0x8803
-#define	CFI_CHIPN_INTEL_28F256K3		"28F256K3"
-#define	CFI_CHIP_INTEL_28F640K18		0x8805
-#define	CFI_CHIPN_INTEL_28F640K18		"28F640K18"
-#define	CFI_CHIP_INTEL_28F128K18		0x8806
-#define	CFI_CHIPN_INTEL_28F128K18		"28F128K18"
-#define	CFI_CHIP_INTEL_28F256K18		0x8807
-#define	CFI_CHIPN_INTEL_28F256K18		"28F256K18"
-
-#endif /* FLASH_INTEL_H */

board/wepep250/lowlevel_init.S

@@ -1,145 +0,0 @@
-/*
- * Copyright (C) 2001, 2002 ETC s.r.o.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version 2
- * of the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA
- * 02111-1307, USA.
- *
- * Written by Marcel Telka <marcel@telka.sk>, 2001, 2002.
- * Changes for U-Boot Peter Figuli <peposh@etc.sk>, 2003.
- *
- * This file is taken from OpenWinCE project hosted by SourceForge.net
- *
- * Documentation:
- * [1] Intel Corporation, "Intel PXA250 and PXA210 Application Processors
- *     Developer's Manual", February 2002, Order Number: 278522-001
- * [2] Samsung Electronics, "8Mx16 SDRAM 54CSP K4S281633D-RL/N/P",
- *     Revision 1.0, February 2002
- * [3] Samsung Electronics, "16Mx16 SDRAM 54CSP K4S561633C-RL(N)",
- *     Revision 1.0, February 2002
- *
-*/
-
-#include <config.h>
-#include <version.h>
-#include <asm/arch/pxa-regs.h>
-
-.globl lowlevel_init
-lowlevel_init:
-
-	mov	r10, lr
-
-/*	setup memory - see 6.12 in [1]
- *	Step 1	- wait 200 us
- */
-	mov	r0,#0x2700			/* wait 200 us @ 99.5 MHz */
-1:	subs	r0, r0, #1
-	bne	1b
-/*	TODO: complete step 1 for Synchronous Static memory*/
-
-	ldr	r0, =0x48000000			/* MC_BASE */
-
-
-/*	step 1.a - setup MSCx
- */
-	ldr	r1, =0x000012B3			/* MSC0_RRR0(1) | MSC0_RDN0(2) | MSC0_RDF0(11) | MSC0_RT0(3) */
-	str	r1, [r0, #0x8]			/* MSC0_OFFSET */
-
-/*	step 1.c - clear MDREFR:K1FREE, set MDREFR:DRI
- *	see AUTO REFRESH chapter in section D. in [2] and in [3]
- *	DRI = (64ms / 4096) * 99.53MHz / 32 = 48 for K4S281633
- *	DRI = (64ms / 8192) * 99.52MHz / 32 = 24 for K4S561633
- *	TODO: complete for Synchronous Static memory
- */
-	ldr	r1, [r0, #4]			/* MDREFR_OFFSET */
-	ldr	r2, =0x01000FFF			/* MDREFR_K1FREE | MDREFR_DRI_MASK */
-	bic	r1, r1, r2
-#if defined( WEP_SDRAM_K4S281633 )
-	orr	r1, r1, #48			/* MDREFR_DRI(48) */
-#elif defined( WEP_SDRAM_K4S561633 )
-	orr	r1, r1, #24			/* MDREFR_DRI(24) */
-#else
-#error SDRAM chip is not defined
-#endif
-
-	str	r1, [r0, #4]			/* MDREFR_OFFSET */
-
-/*	Step 2 - only for Synchronous Static memory (TODO)
- *
- *	Step 3 - same as step 4
- *
- *	Step 4
- *
- *	Step 4.a - set MDREFR:K1RUN, clear MDREFR:K1DB2
- */
-	orr	r1, r1, #0x00010000		/* MDREFR_K1RUN */
-	bic	r1, r1, #0x00020000		/* MDREFR_K1DB2 */
-	str	r1, [r0, #4]			/* MDREFR_OFFSET */
-
-/*	Step 4.b - clear MDREFR:SLFRSH */
-	bic	r1, r1, #0x00400000		/* MDREFR_SLFRSH */
-	str	r1, [r0, #4]			/* MDREFR_OFFSET */
-
-/*	Step 4.c - set MDREFR:E1PIN */
-	orr	r1, r1, #0x00008000		/* MDREFR_E1PIN */
-	str	r1, [r0, #4]			/* MDREFR_OFFSET */
-
-/*	Step 4.d - automatically done
- *
- *	Steps 4.e and 4.f - configure SDRAM
- */
-#if defined( WEP_SDRAM_K4S281633 )
-	ldr	r1, =0x00000AA8			/* MDCNFG_DTC0(2) | MDCNFG_DLATCH0 | MDCNFG_DCAC0(1) | MDCNFG_DRAC0(1) | MDCNFG_DNB0 */
-#elif defined( WEP_SDRAM_K4S561633 )
-	ldr	r1, =0x00000AC8			/* MDCNFG_DTC0(2) | MDCNFG_DLATCH0 | MDCNFG_DCAC0(1) | MDCNFG_DRAC0(2) | MDCNFG_DNB0 */
-#else
-#error SDRAM chip is not defined
-#endif
-	str	r1, [r0, #0]			/* MDCNFG_OFFSET */
-
-/*	Step 5 - wait at least 200 us for SDRAM
- *	see section B. in [2]
- */
-	mov	r2,#0x2700			/* wait 200 us @ 99.5 MHz */
-1:	subs	r2, r2, #1
-	bne	1b
-
-/*	Step 6 - after reset dcache is disabled, so automatically done
- *
- *	Step 7 - eight refresh cycles
- */
-	mov	r2, #0xA0000000
-	ldr	r3, [r2]
-	ldr	r3, [r2]
-	ldr	r3, [r2]
-	ldr	r3, [r2]
-	ldr	r3, [r2]
-	ldr	r3, [r2]
-	ldr	r3, [r2]
-	ldr	r3, [r2]
-
-/*	Step 8 - we don't need dcache now
- *
- *	Step 9 - enable SDRAM partition 0
- */
-	orr	r1, r1, #1			/* MDCNFG_DE0 */
-	str	r1, [r0, #0]			/* MDCNFG_OFFSET */
-
-/*	Step 10 - write MDMRS */
-	mov	r1, #0
-	str	r1, [r0, #0x40]			/* MDMRS_OFFSET */
-
-/*	Step 11 - optional (TODO) */
-
-	mov	pc,r10

board/wepep250/wepep250.c

@@ -1,68 +0,0 @@
-/*
- * Copyright (C) 2003 ETC s.r.o.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- *
- * Written by Peter Figuli <peposh@etc.sk>, 2003.
- *
- */
-
-#include <common.h>
-#include <asm/arch/pxa-regs.h>
-#include <asm/io.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-int board_init (void)
-{
-	gd->bd->bi_arch_number = MACH_TYPE_WEP_EP250;
-	gd->bd->bi_boot_params = 0xa0000000;
-/*
- * Setup GPIO stuff to get serial working
- */
-#if defined( CONFIG_FFUART )
-	writel(0x80, GPDR1);
-	writel(0x8010, GAFR1_L);
-#elif defined( CONFIG_BTUART )
-	writel(0x800, GPDR1);
-	writel(0x900000, GAFR1_L);
-#endif
-	writel(0x20, PSSR);
-
-	return 0;
-}
-
-int dram_init (void)
-{
-#if ( CONFIG_NR_DRAM_BANKS > 0 )
-	gd->bd->bi_dram[0].start = WEP_SDRAM_1;
-	gd->bd->bi_dram[0].size = WEP_SDRAM_1_SIZE;
-#endif
-#if ( CONFIG_NR_DRAM_BANKS > 1 )
-	gd->bd->bi_dram[1].start = WEP_SDRAM_2;
-	gd->bd->bi_dram[1].size = WEP_SDRAM_2_SIZE;
-#endif
-#if ( CONFIG_NR_DRAM_BANKS > 2 )
-	gd->bd->bi_dram[2].start = WEP_SDRAM_3;
-	gd->bd->bi_dram[2].size = WEP_SDRAM_3_SIZE;
-#endif
-#if ( CONFIG_NR_DRAM_BANKS > 3 )
-	gd->bd->bi_dram[3].start = WEP_SDRAM_4;
-	gd->bd->bi_dram[3].size = WEP_SDRAM_4_SIZE;
-#endif
-
-	return 0;
-}

boards.cfg

@@ -401,7 +401,6 @@ lpd7a400	arm	lh7a40x		lpd7a40x
 lpd7a404	arm	lh7a40x		lpd7a40x
 colibri_pxa270	arm	pxa
 pxa255_idp	arm	pxa
-wepep250	arm	pxa
 xsengine	arm	pxa
 zylonite	arm	pxa
 atngw100	avr32	at32ap		-		atmel		at32ap700x

include/configs/wepep250.h

@@ -1,199 +0,0 @@
-/*
- * Copyright (C) 2003 ETC s.r.o.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- *
- * Written by Peter Figuli <peposh@etc.sk>, 2003.
- *
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-#define CONFIG_PXA250          1        /* this is an PXA250 CPU     */
-#define CONFIG_WEPEP250        1        /* config for wepep250 board */
-#undef  CONFIG_USE_IRQ                  /* don't need use IRQ/FIQ    */
-
-/* we will never enable dcache, because we have to setup MMU first */
-#define CONFIG_SYS_NO_DCACHE
-
-/*
- * Select serial console configuration
- */
-#define CONFIG_PXA_SERIAL
-#define CONFIG_BTUART          1       /* BTUART is default on WEP dev board */
-#define CONFIG_BAUDRATE   115200
-
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-
-
-/*
- * Command line configuration.
- */
-#include <config_cmd_default.h>
-
-#undef CONFIG_CMD_CONSOLE
-#undef CONFIG_CMD_LOADS
-#undef CONFIG_CMD_NET
-#undef CONFIG_CMD_SOURCE
-
-
-/*
- * Boot options. Setting delay to -1 stops autostart count down.
- * NOTE: Sending parameters to kernel depends on kernel version and
- * 2.4.19-rmk6-pxa1 patch used while my u-boot coding didn't accept
- * parameters at all! Do not get confused by them so.
- */
-#define CONFIG_BOOTDELAY   -1
-#define CONFIG_BOOTARGS    "root=/dev/mtdblock2 mem=32m console=ttyS01,115200n8"
-#define CONFIG_BOOTCOMMAND "bootm 40000"
-
-
-/*
- * General options for u-boot. Modify to save memory foot print
- */
-#define CONFIG_SYS_LONGHELP                                  /* undef saves memory  */
-#define CONFIG_SYS_PROMPT              "WEP> "               /* prompt string       */
-#define CONFIG_SYS_CBSIZE              256                   /* console I/O buffer  */
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* print buffer size   */
-#define CONFIG_SYS_MAXARGS             16                    /* max command args    */
-#define CONFIG_SYS_BARGSIZE            CONFIG_SYS_CBSIZE            /* boot args buf size  */
-
-#define CONFIG_SYS_MEMTEST_START       0xa0400000            /* memtest test area   */
-#define CONFIG_SYS_MEMTEST_END         0xa0800000
-
-#define CONFIG_SYS_HZ			1000
-#define CONFIG_SYS_CPUSPEED            0x141        /* core clock - register value  */
-
-#define CONFIG_SYS_BAUDRATE_TABLE      { 9600, 19200, 38400, 57600, 115200 }
-
-/*
- * Definitions related to passing arguments to kernel.
- */
-#define CONFIG_CMDLINE_TAG           1   /* send commandline to Kernel       */
-#define CONFIG_SETUP_MEMORY_TAGS     1   /* send memory definition to kernel */
-#undef  CONFIG_INITRD_TAG                /* do not send initrd params        */
-#undef  CONFIG_VFD                       /* do not send framebuffer setup    */
-
-
-/*
- * Malloc pool need to host env + 128 Kb reserve for other allocations.
- */
-#define CONFIG_SYS_MALLOC_LEN	  (CONFIG_ENV_SIZE + (128<<10) )
-#define CONFIG_SYS_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
-
-#define CONFIG_STACKSIZE        (120<<10)      /* stack size */
-
-#ifdef CONFIG_USE_IRQ
-#define CONFIG_STACKSIZE_IRQ    (4<<10)        /* IRQ stack  */
-#define CONFIG_STACKSIZE_FIQ    (4<<10)        /* FIQ stack  */
-#endif
-
-/*
- * SDRAM Memory Map
- */
-#define CONFIG_NR_DRAM_BANKS    1                /* we have 1 bank of SDRAM */
-#define WEP_SDRAM_1            0xa0000000        /* SDRAM bank #1           */
-#define WEP_SDRAM_1_SIZE       0x02000000        /* 32 MB ( 2 chip )        */
-#define WEP_SDRAM_2            0xa2000000        /* SDRAM bank #2           */
-#define WEP_SDRAM_2_SIZE       0x00000000        /* 0 MB                    */
-#define WEP_SDRAM_3            0xa8000000        /* SDRAM bank #3           */
-#define WEP_SDRAM_3_SIZE       0x00000000        /* 0 MB                    */
-#define WEP_SDRAM_4            0xac000000        /* SDRAM bank #4           */
-#define WEP_SDRAM_4_SIZE       0x00000000        /* 0 MB                    */
-
-#define CONFIG_SYS_DRAM_BASE           0xa0000000
-#define CONFIG_SYS_DRAM_SIZE           0x02000000
-
-/* Uncomment used SDRAM chip */
-#define WEP_SDRAM_K4S281633
-/*#define WEP_SDRAM_K4S561633*/
-
-
-/*
- * Configuration for FLASH memory
- */
-#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* FLASH banks count (not chip count)*/
-#define CONFIG_SYS_MAX_FLASH_SECT	128	/* number of sector in FLASH bank    */
-#define WEP_FLASH_BUS_WIDTH	4	/* we use 32 bit FLASH memory...     */
-#define WEP_FLASH_INTERLEAVE	2	/* ... made of 2 chips */
-#define WEP_FLASH_BANK_SIZE  0x2000000  /* size of one flash bank*/
-#define WEP_FLASH_SECT_SIZE  0x0040000  /* size of erase sector */
-#define WEP_FLASH_BASE       0x0000000  /* location of flash memory */
-#define WEP_FLASH_UNLOCK        1       /* perform hw unlock first */
-
-
-/* This should be defined if CFI FLASH device is present. Actually benefit
-   is not so clear to me. In other words we can provide more informations
-   to user, but this expects more complex flash handling we do not provide
-   now.*/
-#undef  CONFIG_SYS_FLASH_CFI
-
-#define CONFIG_SYS_FLASH_ERASE_TOUT    (2*CONFIG_SYS_HZ)    /* timeout for Erase operation */
-#define CONFIG_SYS_FLASH_WRITE_TOUT    (2*CONFIG_SYS_HZ)    /* timeout for Write operation */
-
-#define CONFIG_SYS_FLASH_BASE          WEP_FLASH_BASE
-
-/*
- * This is setting for JFFS2 support in u-boot.
- * Right now there is no gain for user, but later on booting kernel might be
- * possible. Consider using XIP kernel running from flash to save RAM
- * footprint.
- * NOTE: Enable CONFIG_CMD_JFFS2 for JFFS2 support.
- */
-#define CONFIG_SYS_JFFS2_FIRST_BANK		0
-#define CONFIG_SYS_JFFS2_FIRST_SECTOR		5
-#define CONFIG_SYS_JFFS2_NUM_BANKS		1
-
-/*
- * Environment setup. Definitions of monitor location and size with
- * definition of environment setup ends up in 2 possibilities.
- * 1. Embeded environment - in u-boot code is space for environment
- * 2. Environment is read from predefined sector of flash
- * Right now we support 2. possiblity, but expecting no env placed
- * on mentioned address right now. This also needs to provide whole
- * sector for it - for us 256Kb is really waste of memory. U-boot uses
- * default env. and until kernel parameters could be sent to kernel
- * env. has no sense to us.
- */
-
-#define CONFIG_SYS_MONITOR_BASE	PHYS_FLASH_1
-#define CONFIG_SYS_MONITOR_LEN		0x20000		/* 128kb ( 1 flash sector )  */
-#define CONFIG_ENV_IS_IN_FLASH	1
-#define CONFIG_ENV_ADDR		0x20000	        /* absolute address for now  */
-#define CONFIG_ENV_SIZE		0x2000
-
-#define	PHYS_SDRAM_1			WEP_SDRAM_1
-#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM_1
-#define	CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_GBL_DATA_SIZE + PHYS_SDRAM_1)
-
-#undef  CONFIG_ENV_OVERWRITE                    /* env is not writable now   */
-
-/*
- * Well this has to be defined, but on the other hand it is used differently
- * one may expect. For instance loadb command do not cares :-)
- * So advice is - do not relay on this...
- */
-#define CONFIG_SYS_LOAD_ADDR        0x40000
-
-#endif  /* __CONFIG_H */