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@@ -3,7 +3,7 @@
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*
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* Enter bugs at http://blackfin.uclinux.org/
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*
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- * Copyright (c) 2005-2007 Analog Devices Inc.
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+ * Copyright (c) 2005-2008 Analog Devices Inc.
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*
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* Licensed under the GPL-2 or later.
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*/
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@@ -163,7 +163,9 @@ static struct manufacturer_info flash_manufacturers[] = {
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#define TIMEOUT 5000 /* timeout of 5 seconds */
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-/* BF54x support */
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+/* If part has multiple SPI flashes, assume SPI0 as that is
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+ * the one we can boot off of ...
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+ */
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#ifndef pSPI_CTL
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# define pSPI_CTL pSPI0_CTL
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# define pSPI_BAUD pSPI0_BAUD
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@@ -171,19 +173,16 @@ static struct manufacturer_info flash_manufacturers[] = {
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# define pSPI_RDBR pSPI0_RDBR
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# define pSPI_STAT pSPI0_STAT
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# define pSPI_TDBR pSPI0_TDBR
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-# define SPI0_SCK 0x0001
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-# define SPI0_MOSI 0x0004
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-# define SPI0_MISO 0x0002
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-# define SPI0_SEL1 0x0010
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#endif
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/* Default to the SPI SSEL that we boot off of:
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* BF54x, BF537, (everything new?): SSEL1
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- * BF533, BF561: SSEL2
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+ * BF51x, BF533, BF561: SSEL2
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*/
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#ifndef CONFIG_SPI_FLASH_SSEL
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# if defined(__ADSPBF531__) || defined(__ADSPBF532__) || defined(__ADSPBF533__) || \
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- defined(__ADSPBF538__) || defined(__ADSPBF539__) || defined(__ADSPBF561__)
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+ defined(__ADSPBF538__) || defined(__ADSPBF539__) || defined(__ADSPBF561__) || \
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+ defined(__ADSPBF51x__)
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# define CONFIG_SPI_FLASH_SSEL 2
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# else
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# define CONFIG_SPI_FLASH_SSEL 1
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@@ -200,12 +199,15 @@ static void SPI_INIT(void)
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/* enable SPI pins: SSEL, MOSI, MISO, SCK */
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#ifdef __ADSPBF54x__
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- *pPORTE_FER |= (SPI0_SCK | SPI0_MOSI | SPI0_MISO | SPI0_SEL1);
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+ *pPORTE_FER |= (PE0 | PE1 | PE2 | PE4);
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#elif defined(__ADSPBF534__) || defined(__ADSPBF536__) || defined(__ADSPBF537__)
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*pPORTF_FER |= (PF10 | PF11 | PF12 | PF13);
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#elif defined(__ADSPBF52x__)
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bfin_write_PORTG_MUX((bfin_read_PORTG_MUX() & ~PORT_x_MUX_0_MASK) | PORT_x_MUX_0_FUNC_3);
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bfin_write_PORTG_FER(bfin_read_PORTG_FER() | PG1 | PG2 | PG3 | PG4);
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+#elif defined(__ADSPBF51x__)
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+ bfin_write_PORTG_MUX((bfin_read_PORTG_MUX() & ~PORT_x_MUX_7_MASK) | PORT_x_MUX_7_FUNC_1);
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+ bfin_write_PORTG_FER(bfin_read_PORTG_FER() | PG12 | PG13 | PG14 | PG15);
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#endif
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/* initate communication upon write of TDBR */
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Mike Frysinger