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@@ -1912,7 +1912,8 @@ typedef struct ccsr_gur {
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#define MPC85xx_PMUXCR_SD_DATA 0x80000000
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#define MPC85xx_PMUXCR_SDHC_CD 0x40000000
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#define MPC85xx_PMUXCR_SDHC_WP 0x20000000
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- u8 res6[12];
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+ u32 pmuxcr2; /* Alt. function signal multiplex control 2 */
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+ u8 res6[8];
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u32 devdisr; /* Device disable control */
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#define MPC85xx_DEVDISR_PCI1 0x80000000
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#define MPC85xx_DEVDISR_PCI2 0x40000000
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@@ -1949,10 +1950,12 @@ typedef struct ccsr_gur {
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#if defined(CONFIG_MPC8568)||defined(CONFIG_MPC8569)
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u8 res10b[76];
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par_io_t qe_par_io[7];
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- u8 res10c[3136];
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+ u8 res10c[1600];
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#else
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- u8 res10b[3404];
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+ u8 res10b[1868];
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#endif
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+ u32 clkdvdr; /* Clock Divide register */
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+ u8 res10d[1532];
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u32 clkocr; /* Clock out select */
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u8 res11[12];
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u32 ddrdllcr; /* DDR DLL control */
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