Merge branch 'master' of git://www.denx.de/git/u-boot-ppc4xx

MAINTAINERS

@@ -322,6 +322,7 @@ Stefan Roese <sr@denx.de>
 	bunbinga		PPC405EP
 	canyonlands		PPC460EX
 	ebony			PPC440GP
+	glacier			PPC460GT
 	haleakala		PPC405EXr
 	katmai			PPC440SPe
 	kilauea			PPC405EX

MAKEALL

@@ -185,6 +185,7 @@ LIST_4xx="		\
 	ERIC		\
 	EXBITGEN	\
 	G2000		\
+	glacier		\
 	haleakala	\
 	haleakala_nand	\
 	hcu4		\

Makefile

@@ -1172,8 +1172,13 @@ bubinga_config:	unconfig
 CANBT_config:	unconfig
 	@$(MKCONFIG) $(@:_config=) ppc ppc4xx canbt esd
 
-canyonlands_config:	unconfig
-	@$(MKCONFIG) $(@:_config=) ppc ppc4xx canyonlands amcc
+# Canyonlands & Glacier use different U-Boot images
+canyonlands_config \
+glacier_config:	unconfig
+	@mkdir -p $(obj)include
+	@echo "#define CONFIG_$$(echo $(subst ,,$(@:_config=)) | \
+		tr '[:lower:]' '[:upper:]')" >$(obj)include/config.h
+	@$(MKCONFIG) -n $@ -a canyonlands ppc ppc4xx canyonlands amcc
 
 canyonlands_nand_config:	unconfig
 	@mkdir -p $(obj)include $(obj)board/amcc/canyonlands

README

@@ -1929,6 +1929,27 @@ Configuration Settings:
 		Scratch address used by the alternate memory test
 		You only need to set this if address zero isn't writeable
 
+- CFG_MEM_TOP_HIDE (PPC only):
+		If CFG_MEM_TOP_HIDE is defined in the board config header,
+		this specified memory area will get subtracted from the top
+		(end) of ram and won't get "touched" at all by U-Boot. By
+		fixing up gd->ram_size the Linux kernel should gets passed
+		the now "corrected" memory size and won't touch it either.
+		This should work for arch/ppc and arch/powerpc. Only Linux
+		board ports in arch/powerpc with bootwrapper support that
+		recalculate the memory size from the SDRAM controller setup
+		will have to get fixed in Linux additionally.
+
+		This option can be used as a workaround for the 440EPx/GRx
+		CHIP 11 errata where the last 256 bytes in SDRAM shouldn't
+		be touched.
+
+		WARNING: Please make sure that this value is a multiple of
+		the Linux page size (normally 4k). If this is not the case,
+		then the end address of the Linux memory will be located at a
+		non page size aligned address and this could cause major
+		problems.
+
 - CFG_TFTP_LOADADDR:
 		Default load address for network file downloads
 

board/amcc/canyonlands/canyonlands.c

@@ -32,13 +32,20 @@ extern flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */
 
 DECLARE_GLOBAL_DATA_PTR;
 
+#define CFG_BCSR3_PCIE		0x10
+
+#define BOARD_CANYONLANDS_PCIE	1
+#define BOARD_CANYONLANDS_SATA	2
+#define BOARD_GLACIER		3
+
 int board_early_init_f(void)
 {
 	u32 sdr0_cust0;
+	u32 pvr = get_pvr();
 
-	/*------------------------------------------------------------------+
+	/*
 	 * Setup the interrupt controller polarities, triggers, etc.
-	 *------------------------------------------------------------------*/
+	 */
 	mtdcr(uic0sr, 0xffffffff);	/* clear all */
 	mtdcr(uic0er, 0x00000000);	/* disable all */
 	mtdcr(uic0cr, 0x00000005);	/* ATI & UIC1 crit are critical */
@@ -105,27 +112,69 @@ int board_early_init_f(void)
 	mtdcr(AHB_TOP, 0x8000004B);
 	mtdcr(AHB_BOT, 0x8000004B);
 
-	/*
-	 * Configure USB-STP pins as alternate and not GPIO
-	 * It seems to be neccessary to configure the STP pins as GPIO
-	 * input at powerup (perhaps while USB reset is asserted). So
-	 * we configure those pins to their "real" function now.
-	 */
-	gpio_config(16, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1);
-	gpio_config(19, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1);
+	if ((pvr == PVR_460EX_RA) || (pvr == PVR_460EX_SE_RA)) {
+		/*
+		 * Configure USB-STP pins as alternate and not GPIO
+		 * It seems to be neccessary to configure the STP pins as GPIO
+		 * input at powerup (perhaps while USB reset is asserted). So
+		 * we configure those pins to their "real" function now.
+		 */
+		gpio_config(16, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1);
+		gpio_config(19, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1);
+	}
 
 	return 0;
 }
 
-int checkboard (void)
+static void canyonlands_sata_init(int board_type)
+{
+	u32 reg;
+
+	if (board_type == BOARD_CANYONLANDS_SATA) {
+		/* Put SATA in reset */
+		SDR_WRITE(SDR0_SRST1, 0x00020001);
+
+		/* Set the phy for SATA, not PCI-E port 0 */
+		reg = SDR_READ(PESDR0_PHY_CTL_RST);
+		SDR_WRITE(PESDR0_PHY_CTL_RST, (reg & 0xeffffffc) | 0x00000001);
+		reg = SDR_READ(PESDR0_L0CLK);
+		SDR_WRITE(PESDR0_L0CLK, (reg & 0xfffffff8) | 0x00000007);
+		SDR_WRITE(PESDR0_L0CDRCTL, 0x00003111);
+		SDR_WRITE(PESDR0_L0DRV, 0x00000104);
+
+		/* Bring SATA out of reset */
+		SDR_WRITE(SDR0_SRST1, 0x00000000);
+	}
+}
+
+int checkboard(void)
 {
 	char *s = getenv("serial#");
 	u32 pvr = get_pvr();
 
-	if ((pvr == PVR_460GT_RA) || (pvr == PVR_460GT_SE_RA))
+	if ((pvr == PVR_460GT_RA) || (pvr == PVR_460GT_SE_RA)) {
 		printf("Board: Glacier - AMCC PPC460GT Evaluation Board");
-	else
+		gd->board_type = BOARD_GLACIER;
+	} else {
 		printf("Board: Canyonlands - AMCC PPC460EX Evaluation Board");
+		if (in_8((void *)(CFG_BCSR_BASE + 3)) & CFG_BCSR3_PCIE)
+			gd->board_type = BOARD_CANYONLANDS_PCIE;
+		else
+			gd->board_type = BOARD_CANYONLANDS_SATA;
+	}
+
+	switch (gd->board_type) {
+	case BOARD_CANYONLANDS_PCIE:
+	case BOARD_GLACIER:
+		puts(", 2*PCIe");
+		break;
+
+	case BOARD_CANYONLANDS_SATA:
+		puts(", 1*PCIe/1*SATA");
+		break;
+	}
+
+	printf(", Rev. %X", in_8((void *)(CFG_BCSR_BASE + 0)));
 
 	if (s != NULL) {
 		puts(", serial# ");
@@ -133,6 +182,8 @@ int checkboard (void)
 	}
 	putc('\n');
 
+	canyonlands_sata_init(gd->board_type);
+
 	return (0);
 }
 
@@ -198,37 +249,36 @@ int testdram(void)
 }
 #endif
 
-/*************************************************************************
+/*
  *  pci_target_init
  *
  *	The bootstrap configuration provides default settings for the pci
  *	inbound map (PIM). But the bootstrap config choices are limited and
  *	may not be sufficient for a given board.
- *
- ************************************************************************/
+ */
 #if defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT)
 void pci_target_init(struct pci_controller * hose )
 {
-	/*-------------------------------------------------------------------+
+	/*
 	 * Disable everything
-	 *-------------------------------------------------------------------*/
+	 */
 	out_le32((void *)PCIX0_PIM0SA, 0); /* disable */
 	out_le32((void *)PCIX0_PIM1SA, 0); /* disable */
 	out_le32((void *)PCIX0_PIM2SA, 0); /* disable */
 	out_le32((void *)PCIX0_EROMBA, 0); /* disable expansion rom */
 
-	/*-------------------------------------------------------------------+
+	/*
 	 * Map all of SDRAM to PCI address 0x0000_0000. Note that the 440
 	 * strapping options to not support sizes such as 128/256 MB.
-	 *-------------------------------------------------------------------*/
+	 */
 	out_le32((void *)PCIX0_PIM0LAL, CFG_SDRAM_BASE);
 	out_le32((void *)PCIX0_PIM0LAH, 0);
 	out_le32((void *)PCIX0_PIM0SA, ~(gd->ram_size - 1) | 1);
 	out_le32((void *)PCIX0_BAR0, 0);
 
-	/*-------------------------------------------------------------------+
+	/*
 	 * Program the board's subsystem id/vendor id
-	 *-------------------------------------------------------------------*/
+	 */
 	out_le16((void *)PCIX0_SBSYSVID, CFG_PCI_SUBSYS_VENDORID);
 	out_le16((void *)PCIX0_SBSYSID, CFG_PCI_SUBSYS_DEVICEID);
 
@@ -265,13 +315,24 @@ void pcie_setup_hoses(int busno)
 	int ret = 0;
 	char *env;
 	unsigned int delay;
+	int start;
 
 	/*
 	 * assume we're called after the PCIX hose is initialized, which takes
 	 * bus ID 0 and therefore start numbering PCIe's from 1.
 	 */
 	bus = busno;
-	for (i = 0; i <= 1; i++) {
+
+	/*
+	 * Canyonlands with SATA enabled has only one PCIe slot
+	 * (2nd one).
+	 */
+	if (gd->board_type == BOARD_CANYONLANDS_SATA)
+		start = 1;
+	else
+		start = 0;
+
+	for (i = start; i <= 1; i++) {
 
 		if (is_end_point(i))
 			ret = ppc4xx_init_pcie_endport(i);
@@ -369,6 +430,7 @@ int misc_init_r(void)
 {
 	u32 sdr0_srst1 = 0;
 	u32 eth_cfg;
+	u32 pvr = get_pvr();
 
 	/*
 	 * Set EMAC mode/configuration (GMII, SGMII, RGMII...).
@@ -382,7 +444,10 @@ int misc_init_r(void)
 	/* Set the for 2 RGMII mode */
 	/* GMC0 EMAC4_0, GMC0 EMAC4_1, RGMII Bridge 0 */
 	eth_cfg &= ~SDR0_ETH_CFG_GMC0_BRIDGE_SEL;
-	eth_cfg |= SDR0_ETH_CFG_GMC1_BRIDGE_SEL;
+	if ((pvr == PVR_460EX_RA) || (pvr == PVR_460EX_SE_RA))
+		eth_cfg |= SDR0_ETH_CFG_GMC1_BRIDGE_SEL;
+	else
+		eth_cfg &= ~SDR0_ETH_CFG_GMC1_BRIDGE_SEL;
 	mtsdr(SDR0_ETH_CFG, eth_cfg);
 
 	/*
@@ -407,7 +472,7 @@ void ft_board_setup(void *blob, bd_t *bd)
 	/* Fixup NOR mapping */
 	val[0] = 0;				/* chip select number */
 	val[1] = 0;				/* always 0 */
-	val[2] = gd->bd->bi_flashstart;
+	val[2] = CFG_FLASH_BASE_PHYS_L;		/* we fixed up this address */
 	val[3] = gd->bd->bi_flashsize;
 	rc = fdt_find_and_setprop(blob, "/plb/opb/ebc", "ranges",
 				  val, sizeof(val), 1);

board/amcc/canyonlands/u-boot.lds

@@ -139,8 +139,6 @@ SECTIONS
    *(COMMON)
   }
 
-  ppcenv_assert = ASSERT(. < 0xFFFF8000, ".bss section too big, overlaps .ppcenv section. Please update your confguration: CFG_MONITOR_BASE, CFG_MONITOR_LEN and TEXT_BASE may need to be modified.");
-
   _end = . ;
   PROVIDE (end = .);
 }

board/esd/du440/du440.c

@@ -67,12 +67,12 @@ int board_early_init_f(void)
 	out_be32((void*)GPIO1_OR, 0x00000000);
 	out_be32((void*)GPIO1_TCR, 0xc2000000 |
 		 CFG_GPIO1_IORSTN |
+		 CFG_GPIO1_IORST2N |
 		 CFG_GPIO1_LEDUSR1 |
 		 CFG_GPIO1_LEDUSR2 |
 		 CFG_GPIO1_LEDPOST |
 		 CFG_GPIO1_LEDDU);
 	out_be32((void*)GPIO1_ODR, CFG_GPIO1_LEDDU);
-
 	out_be32((void*)GPIO1_OSRL, 0x5c280000);
 	out_be32((void*)GPIO1_OSRH, 0x00000000);
 	out_be32((void*)GPIO1_TSRL, 0x0c000000);
@@ -243,7 +243,8 @@ int misc_init_r(void)
 	 * release IO-RST#
 	 * We have to wait at least 560ms until we may call usbhub_init
 	 */
-	out_be32((void*)GPIO1_OR, in_be32((void*)GPIO1_OR) | CFG_GPIO1_IORSTN);
+	out_be32((void*)GPIO1_OR, in_be32((void*)GPIO1_OR) |
+		 CFG_GPIO1_IORSTN | CFG_GPIO1_IORST2N);
 
 	/*
 	 * flash USR1/2 LEDs (600ms)

board/esd/du440/du440.h

@@ -24,6 +24,7 @@
 #define CFG_GPIO1_DCF77		(0x80000000 >> (42-32))  /* GPIO1_42 */
 
 #define CFG_GPIO1_IORSTN	(0x80000000 >> (55-32))  /* GPIO1_55 */
+#define CFG_GPIO1_IORST2N	(0x80000000 >> (47-32))  /* GPIO1_47 */
 
 #define CFG_GPIO1_HWVER_MASK	0x000000f0 /* GPIO1_56-59 */
 #define CFG_GPIO1_HWVER_SHIFT	4

board/esd/pmc440/cmd_pmc440.c

@@ -1,5 +1,5 @@
 /*
- * (C) Copyright 2007
+ * (C) Copyright 2007-2008
  * Matthias Fuchs, esd Gmbh, matthias.fuchs@esd-electronics.com.
  *
  * See file CREDITS for list of people who contributed to this
@@ -21,7 +21,6 @@
  * MA 02111-1307 USA
  *
  */
-
 #include <common.h>
 #include <command.h>
 #include <asm/io.h>
@@ -31,7 +30,8 @@
 #include "pmc440.h"
 
 int is_monarch(void);
-int bootstrap_eeprom_write(unsigned dev_addr, unsigned offset, uchar *buffer, unsigned cnt);
+int bootstrap_eeprom_write(unsigned dev_addr, unsigned offset,
+			   uchar *buffer, unsigned cnt);
 int eeprom_write_enable(unsigned dev_addr, int state);
 
 DECLARE_GLOBAL_DATA_PTR;
@@ -64,7 +64,6 @@ int fpga_interrupt(u32 arg)
 	return rc;
 }
 
-
 int do_waithci(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 {
 	pmc440_fpga_t *fpga = (pmc440_fpga_t *)FPGA_BA;
@@ -100,7 +99,6 @@ U_BOOT_CMD(
 	NULL
 	);
 
-
 void dump_fifo(pmc440_fpga_t *fpga, int f, int *n)
 {
 	u32 ctrl;
@@ -117,7 +115,6 @@ void dump_fifo(pmc440_fpga_t *fpga, int f, int *n)
 	}
 }
 
-
 int do_fifo(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 {
 	pmc440_fpga_t *fpga = (pmc440_fpga_t *)FPGA_BA;
@@ -200,7 +197,8 @@ int do_fifo(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 					got_fifoirq = 0;
 					/* unmask global fifo irq */
 					FPGA_OUT32(&fpga->hostctrl,
-						   HOSTCTRL_FIFOIE_GATE | HOSTCTRL_FIFOIE_FLAG);
+						   HOSTCTRL_FIFOIE_GATE |
+						   HOSTCTRL_FIFOIE_FLAG);
 				}
 			}
 
@@ -237,7 +235,8 @@ int do_fifo(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 				for (i=0; i<n; i++)
 					FPGA_OUT32(&fpga->fifo[f].data, data);
 			} else {
-				printf("writing %d x %08x to fifo port at address %08x\n",
+				printf("writing %d x %08x to fifo port at "
+				       "address %08x\n",
 				       n, data, f);
 				for (i=0; i<n; i++)
 					out32(f, data);
@@ -263,10 +262,10 @@ U_BOOT_CMD(
 	"  - without arguments: print all fifo's status\n"
 	"  - with 'wait' argument: interrupt driven read from all fifos\n"
 	"  - with 'read' argument: read current contents from all fifos\n"
-	"  - with 'write' argument: write 'data' 'cnt' times to 'fifo' or 'address'\n"
+	"  - with 'write' argument: write 'data' 'cnt' times to "
+	"'fifo' or 'address'\n"
 	);
 
-
 int do_setup_bootstrap_eeprom(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 {
 	ulong sdsdp[5];
@@ -301,10 +300,12 @@ int do_setup_bootstrap_eeprom(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]
 			sdsdp[2]=0x40082350;
 			sdsdp[3]=0x0d050000;
 		} else if (!strcmp(argv[1], "test")) {
-			/* TODO: this will replace the 667 MHz config above.
+			/*
+			 * TODO: this will replace the 667 MHz config above.
 			 * But it needs some more testing on a real 667 MHz CPU.
 			 */
-			printf("Bootstrapping for test (667MHz PLB=133PLB PLB/PCI=3)\n");
+			printf("Bootstrapping for test"
+			       " (667MHz PLB=133PLB PLB/PCI=3)\n");
 			sdsdp[0]=0x8778a256;
 			sdsdp[1]=0x095fa030;
 			sdsdp[2]=0x40082350;
@@ -347,7 +348,6 @@ U_BOOT_CMD(
 	"<cpufreq:400|533|667> [<console-uart:0|1> [<bringup delay (0..20s)>]]"
 	);
 
-
 #if defined(CONFIG_PRAM)
 #include <environment.h>
 extern env_t *env_ptr;
@@ -394,7 +394,6 @@ U_BOOT_CMD(
 	);
 #endif /* CONFIG_PRAM */
 
-
 int do_selfreset(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 {
 	if (argc > 1) {
@@ -423,7 +422,6 @@ U_BOOT_CMD(
 	NULL
 	);
 
-
 int do_resetout(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 {
 	pmc440_fpga_t *fpga = (pmc440_fpga_t *)FPGA_BA;
@@ -444,7 +442,8 @@ int do_resetout(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 			/* deassert */
 			printf("PMC-RESETOUT# deasserted\n");
 			FPGA_OUT32(&fpga->hostctrl,
-				   HOSTCTRL_PMCRSTOUT_GATE | HOSTCTRL_PMCRSTOUT_FLAG);
+				   HOSTCTRL_PMCRSTOUT_GATE |
+				   HOSTCTRL_PMCRSTOUT_FLAG);
 		}
 	} else {
 		printf("PMC-RESETOUT# is %s\n",
@@ -460,7 +459,6 @@ U_BOOT_CMD(
 	NULL
 	);
 
-
 int do_inta(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 {
 	if (is_monarch()) {
@@ -481,7 +479,9 @@ int do_inta(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 				 in_be32((void*)GPIO1_TCR) & ~GPIO1_INTA_FAKE);
 		}
 	} else {
-		printf("inta# is %s\n", in_be32((void*)GPIO1_TCR) & GPIO1_INTA_FAKE ? "active" : "inactive");
+		printf("inta# is %s\n",
+		       in_be32((void*)GPIO1_TCR) & GPIO1_INTA_FAKE ?
+		       "active" : "inactive");
 	}
 	return 0;
 }
@@ -491,7 +491,6 @@ U_BOOT_CMD(
 	NULL
 	);
 
-
 /* test-only */
 int do_pmm(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 {
@@ -503,11 +502,17 @@ int do_pmm(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 		pciaddr &= 0xf0000000;
 
 		/* map PCI address at 0xc0000000 in PLB space */
-		out32r(PCIX0_PMM1MA, 0x00000000); /* PMM1 Mask/Attribute - disabled b4 setting */
-		out32r(PCIX0_PMM1LA, 0xc0000000); /* PMM1 Local Address */
-		out32r(PCIX0_PMM1PCILA, pciaddr); /* PMM1 PCI Low Address */
-		out32r(PCIX0_PMM1PCIHA, 0x00000000); /* PMM1 PCI High Address */
-		out32r(PCIX0_PMM1MA, 0xf0000001); /* 256MB + No prefetching, and enable region */
+
+		/* PMM1 Mask/Attribute - disabled b4 setting */
+		out32r(PCIX0_PMM1MA, 0x00000000);
+		/* PMM1 Local Address */
+		out32r(PCIX0_PMM1LA, 0xc0000000);
+		/* PMM1 PCI Low Address */
+		out32r(PCIX0_PMM1PCILA, pciaddr);
+		/* PMM1 PCI High Address */
+		out32r(PCIX0_PMM1PCIHA, 0x00000000);
+		/* 256MB + No prefetching, and enable region */
+		out32r(PCIX0_PMM1MA, 0xf0000001);
 	} else {
 		printf("Usage:\npmm %s\n", cmdtp->help);
 	}

board/esd/pmc440/pmc440.c

@@ -1,5 +1,5 @@
 /*
- * (C) Copyright 2007
+ * (C) Copyright 2007-2008
  * Matthias Fuchs, esd gmbh, matthias.fuchs@esd-electronics.com.
  * Based on board/amcc/sequoia/sequoia.c
  *
@@ -32,6 +32,7 @@
 #include <ppc440.h>
 #include <asm/processor.h>
 #include <asm/io.h>
+#include <asm/bitops.h>
 #include <command.h>
 #include <i2c.h>
 #ifdef CONFIG_RESET_PHY_R
@@ -43,12 +44,12 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
-extern flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips	*/
+extern flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */
 
 ulong flash_get_size(ulong base, int banknum);
 int pci_is_66mhz(void);
-int bootstrap_eeprom_read(unsigned dev_addr, unsigned offset, uchar *buffer, unsigned cnt);
-
+int bootstrap_eeprom_read(unsigned dev_addr, unsigned offset,
+			  uchar *buffer, unsigned cnt);
 
 struct serial_device *default_serial_console(void)
 {
@@ -70,7 +71,8 @@ struct serial_device *default_serial_console(void)
 		/* mark scratchreg valid */
 		scratchreg = (scratchreg & 0xffffff00) | 0x80;
 
-		i = bootstrap_eeprom_read(CFG_I2C_BOOT_EEPROM_ADDR, 0x10, buf, 4);
+		i = bootstrap_eeprom_read(CFG_I2C_BOOT_EEPROM_ADDR,
+					  0x10, buf, 4);
 		if ((i != -1) && (buf[0] == 0x19) && (buf[1] == 0x75)) {
 			scratchreg |= buf[2];
 
@@ -99,10 +101,10 @@ int board_early_init_f(void)
 	mtdcr(ebccfga, xbcfg);
 	mtdcr(ebccfgd, 0xf8400000);
 
-	/*--------------------------------------------------------------------
+	/*
 	 * Setup the GPIO pins
 	 * TODO: setup GPIOs via CFG_4xx_GPIO_TABLE in board's config file
-	 *-------------------------------------------------------------------*/
+	 */
 	out32(GPIO0_OR,    0x40000002);
 	out32(GPIO0_TCR,   0x4c90011f);
 	out32(GPIO0_OSRL,  0x28011400);
@@ -141,9 +143,9 @@ int board_early_init_f(void)
 		mtspr(dbcr0, 0x20000000); /* do chip reset */
 	}
 
-	/*--------------------------------------------------------------------
+	/*
 	 * Setup the interrupt controller polarities, triggers, etc.
-	 *-------------------------------------------------------------------*/
+	 */
 	mtdcr(uic0sr, 0xffffffff);	/* clear all */
 	mtdcr(uic0er, 0x00000000);	/* disable all */
 	mtdcr(uic0cr, 0x00000005);	/* ATI & UIC1 crit are critical */
@@ -170,9 +172,11 @@ int board_early_init_f(void)
 
 	/* select Ethernet pins */
 	mfsdr(SDR0_PFC1, sdr0_pfc1);
-	sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_SELECT_MASK) | SDR0_PFC1_SELECT_CONFIG_4;
+	sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_SELECT_MASK) |
+		SDR0_PFC1_SELECT_CONFIG_4;
 	mfsdr(SDR0_PFC2, sdr0_pfc2);
-	sdr0_pfc2 = (sdr0_pfc2 & ~SDR0_PFC2_SELECT_MASK) | SDR0_PFC2_SELECT_CONFIG_4;
+	sdr0_pfc2 = (sdr0_pfc2 & ~SDR0_PFC2_SELECT_MASK) |
+		SDR0_PFC2_SELECT_CONFIG_4;
 
 	/* enable 2nd IIC */
 	sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_SIS_MASK) | SDR0_PFC1_SIS_IIC1_SEL;
@@ -192,9 +196,9 @@ int board_early_init_f(void)
 	return 0;
 }
 
-/*---------------------------------------------------------------------------+
-  | misc_init_r.
-  +---------------------------------------------------------------------------*/
+/*
+ * misc_init_r.
+ */
 int misc_init_r(void)
 {
 	uint pbcr;
@@ -221,32 +225,7 @@ int misc_init_r(void)
 	mtdcr(ebccfga, pb0cr);
 #endif
 	pbcr = mfdcr(ebccfgd);
-	switch (gd->bd->bi_flashsize) {
-	case 1 << 20:
-		size_val = 0;
-		break;
-	case 2 << 20:
-		size_val = 1;
-		break;
-	case 4 << 20:
-		size_val = 2;
-		break;
-	case 8 << 20:
-		size_val = 3;
-		break;
-	case 16 << 20:
-		size_val = 4;
-		break;
-	case 32 << 20:
-		size_val = 5;
-		break;
-	case 64 << 20:
-		size_val = 6;
-		break;
-	case 128 << 20:
-		size_val = 7;
-		break;
-	}
+	size_val = ffs(gd->bd->bi_flashsize) - 21;
 	pbcr = (pbcr & 0x0001ffff) | gd->bd->bi_flashstart | (size_val << 17);
 #if defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL)
 	mtdcr(ebccfga, pb2cr);
@@ -286,20 +265,22 @@ int misc_init_r(void)
 		mfsdr(SDR0_USB2H0CR, usb2h0cr);
 
 		usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_XOCLK_MASK;
-		usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_XOCLK_EXTERNAL;	/*0*/
+		usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_XOCLK_EXTERNAL;
 		usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_WDINT_MASK;
-		usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_WDINT_16BIT_30MHZ;	/*1*/
+		usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_WDINT_16BIT_30MHZ;
 		usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DVBUS_MASK;
-		usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DVBUS_PURDIS;		/*0*/
+		usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DVBUS_PURDIS;
 		usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DWNSTR_MASK;
-		usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DWNSTR_HOST;		/*1*/
+		usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DWNSTR_HOST;
 		usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_UTMICN_MASK;
-		usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_UTMICN_HOST;		/*1*/
+		usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_UTMICN_HOST;
 
-		/* An 8-bit/60MHz interface is the only possible alternative
-		   when connecting the Device to the PHY */
+		/*
+		 * An 8-bit/60MHz interface is the only possible alternative
+		 * when connecting the Device to the PHY
+		 */
 		usb2h0cr   = usb2h0cr &~SDR0_USB2H0CR_WDINT_MASK;
-		usb2h0cr   = usb2h0cr | SDR0_USB2H0CR_WDINT_16BIT_30MHZ;	/*1*/
+		usb2h0cr   = usb2h0cr | SDR0_USB2H0CR_WDINT_16BIT_30MHZ;
 
 		usb2d0cr = usb2d0cr &~SDR0_USB2D0CR_USB2DEV_EBC_SEL_MASK;
 		sdr0_pfc1 = sdr0_pfc1 &~SDR0_PFC1_UES_MASK;
@@ -309,7 +290,7 @@ int misc_init_r(void)
 		mtsdr(SDR0_USB2PHY0CR, usb2phy0cr);
 		mtsdr(SDR0_USB2H0CR, usb2h0cr);
 
-		/*clear resets*/
+		/* clear resets */
 		udelay(1000);
 		mtsdr(SDR0_SRST1, 0x00000000);
 		udelay(1000);
@@ -317,18 +298,18 @@ int misc_init_r(void)
 
 		printf("USB:   Host\n");
 
-	} else if ((strcmp(act, "dev") == 0) || (in_be32((void*)GPIO0_IR) & GPIO0_USB_PRSNT)) {
-		/*-------------------PATCH-------------------------------*/
+	} else if ((strcmp(act, "dev") == 0) ||
+		   (in_be32((void*)GPIO0_IR) & GPIO0_USB_PRSNT)) {
 		mfsdr(SDR0_USB2PHY0CR, usb2phy0cr);
 
 		usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_XOCLK_MASK;
-		usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_XOCLK_EXTERNAL;	/*0*/
+		usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_XOCLK_EXTERNAL;
 		usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DVBUS_MASK;
-		usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DVBUS_PURDIS;		/*0*/
+		usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DVBUS_PURDIS;
 		usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DWNSTR_MASK;
-		usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DWNSTR_HOST;		/*1*/
+		usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DWNSTR_HOST;
 		usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_UTMICN_MASK;
-		usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_UTMICN_HOST;		/*1*/
+		usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_UTMICN_HOST;
 		mtsdr(SDR0_USB2PHY0CR, usb2phy0cr);
 
 		udelay (1000);
@@ -344,7 +325,6 @@ int misc_init_r(void)
 
 		udelay (1000);
 		mtsdr(SDR0_SRST1, 0x60306000);
-		/*-------------------PATCH-------------------------------*/
 
 		/* SDR Setting */
 		mfsdr(SDR0_USB2PHY0CR, usb2phy0cr);
@@ -353,23 +333,23 @@ int misc_init_r(void)
 		mfsdr(SDR0_PFC1, sdr0_pfc1);
 
 		usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_XOCLK_MASK;
-		usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_XOCLK_EXTERNAL;	/*0*/
+		usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_XOCLK_EXTERNAL;
 		usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_WDINT_MASK;
-		usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_WDINT_8BIT_60MHZ;	/*0*/
+		usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_WDINT_8BIT_60MHZ;
 		usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DVBUS_MASK;
-		usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DVBUS_PUREN;		/*1*/
+		usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DVBUS_PUREN;
 		usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DWNSTR_MASK;
-		usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DWNSTR_DEV;		/*0*/
+		usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DWNSTR_DEV;
 		usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_UTMICN_MASK;
-		usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_UTMICN_DEV;		/*0*/
+		usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_UTMICN_DEV;
 
 		usb2h0cr   = usb2h0cr &~SDR0_USB2H0CR_WDINT_MASK;
-		usb2h0cr   = usb2h0cr | SDR0_USB2H0CR_WDINT_8BIT_60MHZ;		/*0*/
+		usb2h0cr   = usb2h0cr | SDR0_USB2H0CR_WDINT_8BIT_60MHZ;
 
 		usb2d0cr = usb2d0cr &~SDR0_USB2D0CR_USB2DEV_EBC_SEL_MASK;
 
 		sdr0_pfc1 = sdr0_pfc1 &~SDR0_PFC1_UES_MASK;
-		sdr0_pfc1 = sdr0_pfc1 | SDR0_PFC1_UES_EBCHR_SEL;		/*1*/
+		sdr0_pfc1 = sdr0_pfc1 | SDR0_PFC1_UES_EBCHR_SEL;
 
 		mtsdr(SDR0_USB2H0CR, usb2h0cr);
 		mtsdr(SDR0_USB2PHY0CR, usb2phy0cr);
@@ -453,43 +433,42 @@ void pmc440_pci_fixup_irq(struct pci_controller *hose, pci_dev_t dev)
 }
 #endif
 
-/*************************************************************************
- *  pci_pre_init
- *
- *  This routine is called just prior to registering the hose and gives
- *  the board the opportunity to check things. Returning a value of zero
- *  indicates that things are bad & PCI initialization should be aborted.
+/*
+ * pci_pre_init
  *
- *	Different boards may wish to customize the pci controller structure
- *	(add regions, override default access routines, etc) or perform
- *	certain pre-initialization actions.
+ * This routine is called just prior to registering the hose and gives
+ * the board the opportunity to check things. Returning a value of zero
+ * indicates that things are bad & PCI initialization should be aborted.
  *
- ************************************************************************/
+ * Different boards may wish to customize the pci controller structure
+ * (add regions, override default access routines, etc) or perform
+ * certain pre-initialization actions.
+ */
 #if defined(CONFIG_PCI)
 int pci_pre_init(struct pci_controller *hose)
 {
 	unsigned long addr;
 
-	/*-------------------------------------------------------------------------+
-	  | Set priority for all PLB3 devices to 0.
-	  | Set PLB3 arbiter to fair mode.
-	  +-------------------------------------------------------------------------*/
+	/*
+	 * Set priority for all PLB3 devices to 0.
+	 * Set PLB3 arbiter to fair mode.
+	 */
 	mfsdr(sdr_amp1, addr);
 	mtsdr(sdr_amp1, (addr & 0x000000FF) | 0x0000FF00);
 	addr = mfdcr(plb3_acr);
 	mtdcr(plb3_acr, addr | 0x80000000);
 
-	/*-------------------------------------------------------------------------+
-	  | Set priority for all PLB4 devices to 0.
-	  +-------------------------------------------------------------------------*/
+	/*
+	 * Set priority for all PLB4 devices to 0.
+	 */
 	mfsdr(sdr_amp0, addr);
 	mtsdr(sdr_amp0, (addr & 0x000000FF) | 0x0000FF00);
 	addr = mfdcr(plb4_acr) | 0xa0000000;	/* Was 0x8---- */
 	mtdcr(plb4_acr, addr);
 
-	/*-------------------------------------------------------------------------+
-	  | Set Nebula PLB4 arbiter to fair mode.
-	  +-------------------------------------------------------------------------*/
+	/*
+	 * Set Nebula PLB4 arbiter to fair mode.
+	 */
 	/* Segment0 */
 	addr = (mfdcr(plb0_acr) & ~plb0_acr_ppm_mask) | plb0_acr_ppm_fair;
 	addr = (addr & ~plb0_acr_hbu_mask) | plb0_acr_hbu_enabled;
@@ -512,64 +491,84 @@ int pci_pre_init(struct pci_controller *hose)
 }
 #endif /* defined(CONFIG_PCI) */
 
-/*************************************************************************
- *  pci_target_init
- *
- *	The bootstrap configuration provides default settings for the pci
- *	inbound map (PIM). But the bootstrap config choices are limited and
- *	may not be sufficient for a given board.
+/*
+ * pci_target_init
  *
- ************************************************************************/
+ * The bootstrap configuration provides default settings for the pci
+ * inbound map (PIM). But the bootstrap config choices are limited and
+ * may not be sufficient for a given board.
+ */
 #if defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT)
 void pci_target_init(struct pci_controller *hose)
 {
-	/*--------------------------------------------------------------------------+
+	char *ptmla_str, *ptmms_str;
+
+	/*
 	 * Set up Direct MMIO registers
-	 *--------------------------------------------------------------------------*/
-	/*--------------------------------------------------------------------------+
-	  | PowerPC440EPX PCI Master configuration.
-	  | Map one 1Gig range of PLB/processor addresses to PCI memory space.
-	  |   PLB address 0x80000000-0xBFFFFFFF ==> PCI address 0x80000000-0xBFFFFFFF
-	  |   Use byte reversed out routines to handle endianess.
-	  | Make this region non-prefetchable.
-	  +--------------------------------------------------------------------------*/
-	out32r(PCIX0_PMM0MA, 0x00000000);	/* PMM0 Mask/Attribute - disabled b4 setting */
+	 */
+	/*
+	 * PowerPC440EPX PCI Master configuration.
+	 * Map one 1Gig range of PLB/processor addresses to PCI memory space.
+	 * PLB address 0x80000000-0xBFFFFFFF
+	 *     ==> PCI address 0x80000000-0xBFFFFFFF
+	 * Use byte reversed out routines to handle endianess.
+	 * Make this region non-prefetchable.
+	 */
+	out32r(PCIX0_PMM0MA, 0x00000000);	/* PMM0 Mask/Attribute */
+						/* - disabled b4 setting */
 	out32r(PCIX0_PMM0LA, CFG_PCI_MEMBASE);	/* PMM0 Local Address */
-	out32r(PCIX0_PMM0PCILA, CFG_PCI_MEMBASE);	/* PMM0 PCI Low Address */
+	out32r(PCIX0_PMM0PCILA, CFG_PCI_MEMBASE); /* PMM0 PCI Low Address */
 	out32r(PCIX0_PMM0PCIHA, 0x00000000);	/* PMM0 PCI High Address */
-	out32r(PCIX0_PMM0MA, 0xc0000001);	/* 1G + No prefetching, and enable region */
+	out32r(PCIX0_PMM0MA, 0xc0000001);	/* 1G + No prefetching, */
+						/* and enable region */
 
 	if (!is_monarch()) {
-		/* BAR1: top 64MB of RAM */
-		out32r(PCIX0_PTM1MS, 0xfc000001);	/* Memory Size/Attribute */
-		out32r(PCIX0_PTM1LA, 0x0c000000);       /* Local Addr. Reg */
+		ptmla_str = getenv("ptm1la");
+		ptmms_str = getenv("ptm1ms");
+		if(NULL != ptmla_str && NULL != ptmms_str ) {
+			out32r(PCIX0_PTM1MS,
+			       simple_strtoul(ptmms_str, NULL, 16));
+			out32r(PCIX0_PTM1LA,
+			       simple_strtoul(ptmla_str, NULL, 16));
+		} else {
+			/* BAR1: default top 64MB of RAM */
+			out32r(PCIX0_PTM1MS, 0xfc000001);
+			out32r(PCIX0_PTM1LA, 0x0c000000);
+		}
 	} else {
-		/* BAR1: complete 256MB RAM (TODO: make dynamic) */
-		out32r(PCIX0_PTM1MS, 0xf0000001);	/* Memory Size/Attribute */
-		out32r(PCIX0_PTM1LA, 0x00000000);       /* Local Addr. Reg */
+		/* BAR1: default: complete 256MB RAM */
+		out32r(PCIX0_PTM1MS, 0xf0000001);
+		out32r(PCIX0_PTM1LA, 0x00000000);
 	}
 
-	/* BAR2: 16 MB FPGA registers */
-	out32r(PCIX0_PTM2MS, 0xff000001);	/* Memory Size/Attribute */
-	out32r(PCIX0_PTM2LA, 0xef000000);	/* Local Addr. Reg */
+	ptmla_str = getenv("ptm2la");		/* Local Addr. Reg */
+	ptmms_str = getenv("ptm2ms");		/* Memory Size/Attribute */
+	if(NULL != ptmla_str && NULL != ptmms_str ) {
+		out32r(PCIX0_PTM2MS, simple_strtoul(ptmms_str, NULL, 16));
+		out32r(PCIX0_PTM2LA, simple_strtoul(ptmla_str, NULL, 16));
+	} else {
+		/* BAR2: default: 16 MB FPGA + registers */
+		out32r(PCIX0_PTM2MS, 0xff000001); /* Memory Size/Attribute */
+		out32r(PCIX0_PTM2LA, 0xef000000); /* Local Addr. Reg */
+	}
 
 	if (is_monarch()) {
 		/* BAR2: map FPGA registers behind system memory at 1GB */
 		pci_write_config_dword(0, PCI_BASE_ADDRESS_2, 0x40000008);
 	}
 
-	/*--------------------------------------------------------------------------+
+	/*
 	 * Set up Configuration registers
-	 *--------------------------------------------------------------------------*/
+	 */
 
 	/* Program the board's vendor id */
 	pci_write_config_word(0, PCI_SUBSYSTEM_VENDOR_ID,
 			      CFG_PCI_SUBSYS_VENDORID);
 
-#if 0   /* disabled for PMC405 backward compatibility */
+	/* disabled for PMC405 backward compatibility */
 	/* Configure command register as bus master */
-	pci_write_config_word(0, PCI_COMMAND, PCI_COMMAND_MASTER);
-#endif
+	/* pci_write_config_word(0, PCI_COMMAND, PCI_COMMAND_MASTER); */
+
 
 	/* 240nS PCI clock */
 	pci_write_config_word(0, PCI_LATENCY_TIMER, 1);
@@ -587,8 +586,10 @@ void pci_target_init(struct pci_controller *hose)
 				      CFG_PCI_CLASSCODE_NONMONARCH);
 
 		/* PCI configuration done: release ERREADY */
-		out_be32((void*)GPIO1_OR,  in_be32((void*)GPIO1_OR)  | GPIO1_PPC_EREADY);
-		out_be32((void*)GPIO1_TCR, in_be32((void*)GPIO1_TCR) | GPIO1_PPC_EREADY);
+		out_be32((void*)GPIO1_OR,
+			 in_be32((void*)GPIO1_OR) | GPIO1_PPC_EREADY);
+		out_be32((void*)GPIO1_TCR,
+			 in_be32((void*)GPIO1_TCR) | GPIO1_PPC_EREADY);
 	} else {
 		/* Program the board's subsystem id/classcode */
 		pci_write_config_word(0, PCI_SUBSYSTEM_ID,
@@ -599,20 +600,19 @@ void pci_target_init(struct pci_controller *hose)
 }
 #endif /* defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) */
 
-/*************************************************************************
- *  pci_master_init
- *
- ************************************************************************/
+/*
+ * pci_master_init
+ */
 #if defined(CONFIG_PCI) && defined(CFG_PCI_MASTER_INIT)
 void pci_master_init(struct pci_controller *hose)
 {
 	unsigned short temp_short;
 
-	/*--------------------------------------------------------------------------+
-	  | Write the PowerPC440 EP PCI Configuration regs.
-	  |   Enable PowerPC440 EP to be a master on the PCI bus (PMM).
-	  |   Enable PowerPC440 EP to act as a PCI memory target (PTM).
-	  +--------------------------------------------------------------------------*/
+	/*
+	 * Write the PowerPC440 EP PCI Configuration regs.
+	 * Enable PowerPC440 EP to be a master on the PCI bus (PMM).
+	 * Enable PowerPC440 EP to act as a PCI memory target (PTM).
+	 */
 	if (is_monarch()) {
 		pci_read_config_word(0, PCI_COMMAND, &temp_short);
 		pci_write_config_word(0, PCI_COMMAND,
@@ -622,7 +622,6 @@ void pci_master_init(struct pci_controller *hose)
 }
 #endif /* defined(CONFIG_PCI) && defined(CFG_PCI_MASTER_INIT) */
 
-
 static void wait_for_pci_ready(void)
 {
 	int i;
@@ -649,22 +648,19 @@ static void wait_for_pci_ready(void)
 	}
 }
 
-
-/*************************************************************************
- *  is_pci_host
- *
- *	This routine is called to determine if a pci scan should be
- *	performed. With various hardware environments (especially cPCI and
- *	PPMC) it's insufficient to depend on the state of the arbiter enable
- *	bit in the strap register, or generic host/adapter assumptions.
- *
- *	Rather than hard-code a bad assumption in the general 440 code, the
- *	440 pci code requires the board to decide at runtime.
+/*
+ * is_pci_host
  *
- *	Return 0 for adapter mode, non-zero for host (monarch) mode.
+ * This routine is called to determine if a pci scan should be
+ * performed. With various hardware environments (especially cPCI and
+ * PPMC) it's insufficient to depend on the state of the arbiter enable
+ * bit in the strap register, or generic host/adapter assumptions.
  *
+ * Rather than hard-code a bad assumption in the general 440 code, the
+ * 440 pci code requires the board to decide at runtime.
  *
- ************************************************************************/
+ * Return 0 for adapter mode, non-zero for host (monarch) mode.
+ */
 #if defined(CONFIG_PCI)
 int is_pci_host(struct pci_controller *hose)
 {
@@ -681,6 +677,7 @@ int is_pci_host(struct pci_controller *hose)
 	return 0;
 }
 #endif /* defined(CONFIG_PCI) */
+
 #if defined(CONFIG_POST)
 /*
  * Returns 1 if keys pressed to start the power-on long-running tests
@@ -692,7 +689,6 @@ int post_hotkeys_pressed(void)
 }
 #endif /* CONFIG_POST */
 
-
 #ifdef CONFIG_RESET_PHY_R
 void reset_phy(void)
 {
@@ -713,17 +709,19 @@ void reset_phy(void)
 #endif
 
 #if defined(CFG_EEPROM_WREN)
-/* Input: <dev_addr>  I2C address of EEPROM device to enable.
- *         <state>     -1: deliver current state
+/*
+ *  Input: <dev_addr> I2C address of EEPROM device to enable.
+ *         <state>    -1: deliver current state
  *	               0: disable write
  *		       1: enable write
- *  Returns:           -1: wrong device address
- *                      0: dis-/en- able done
+ *  Returns:          -1: wrong device address
+ *                     0: dis-/en- able done
  *		     0/1: current state if <state> was -1.
  */
 int eeprom_write_enable(unsigned dev_addr, int state)
 {
-	if ((CFG_I2C_EEPROM_ADDR != dev_addr) && (CFG_I2C_BOOT_EEPROM_ADDR != dev_addr)) {
+	if ((CFG_I2C_EEPROM_ADDR != dev_addr) &&
+	    (CFG_I2C_BOOT_EEPROM_ADDR != dev_addr)) {
 		return -1;
 	} else {
 		switch (state) {
@@ -747,9 +745,9 @@ int eeprom_write_enable(unsigned dev_addr, int state)
 }
 #endif /* #if defined(CFG_EEPROM_WREN) */
 
-
 #define CFG_BOOT_EEPROM_PAGE_WRITE_BITS 3
-int bootstrap_eeprom_write(unsigned dev_addr, unsigned offset, uchar *buffer, unsigned cnt)
+int bootstrap_eeprom_write(unsigned dev_addr, unsigned offset,
+			   uchar *buffer, unsigned cnt)
 {
 	unsigned end = offset + cnt;
 	unsigned blk_off;
@@ -758,7 +756,8 @@ int bootstrap_eeprom_write(unsigned dev_addr, unsigned offset, uchar *buffer, un
 #if defined(CFG_EEPROM_WREN)
 	eeprom_write_enable(dev_addr, 1);
 #endif
-	/* Write data until done or would cross a write page boundary.
+	/*
+	 * Write data until done or would cross a write page boundary.
 	 * We must write the address again when changing pages
 	 * because the address counter only increments within a page.
 	 */
@@ -780,7 +779,8 @@ int bootstrap_eeprom_write(unsigned dev_addr, unsigned offset, uchar *buffer, un
 #define	BOOT_EEPROM_PAGE_SIZE	   (1 << CFG_BOOT_EEPROM_PAGE_WRITE_BITS)
 #define	BOOT_EEPROM_PAGE_OFFSET(x) ((x) & (BOOT_EEPROM_PAGE_SIZE - 1))
 
-		maxlen = BOOT_EEPROM_PAGE_SIZE - BOOT_EEPROM_PAGE_OFFSET(blk_off);
+		maxlen = BOOT_EEPROM_PAGE_SIZE -
+			BOOT_EEPROM_PAGE_OFFSET(blk_off);
 		if (maxlen > I2C_RXTX_LEN)
 			maxlen = I2C_RXTX_LEN;
 
@@ -803,14 +803,15 @@ int bootstrap_eeprom_write(unsigned dev_addr, unsigned offset, uchar *buffer, un
 	return rcode;
 }
 
-
-int bootstrap_eeprom_read (unsigned dev_addr, unsigned offset, uchar *buffer, unsigned cnt)
+int bootstrap_eeprom_read (unsigned dev_addr, unsigned offset,
+			   uchar *buffer, unsigned cnt)
 {
 	unsigned end = offset + cnt;
 	unsigned blk_off;
 	int rcode = 0;
 
-	/* Read data until done or would cross a page boundary.
+	/*
+	 * Read data until done or would cross a page boundary.
 	 * We must write the address again when changing pages
 	 * because the next page may be in a different device.
 	 */
@@ -844,7 +845,6 @@ int bootstrap_eeprom_read (unsigned dev_addr, unsigned offset, uchar *buffer, un
 	return rcode;
 }
 
-
 #if defined(CONFIG_USB_OHCI_NEW) && defined(CFG_USB_OHCI_BOARD_INIT)
 int usb_board_init(void)
 {
@@ -854,7 +854,8 @@ int usb_board_init(void)
 	if ((act == NULL || strcmp(act, "hostdev") == 0) &&
 	    !(in_be32((void*)GPIO0_IR) & GPIO0_USB_PRSNT))
 		/* enable power on USB socket */
-		out_be32((void*)GPIO1_OR, in_be32((void*)GPIO1_OR) & ~GPIO1_USB_PWR_N);
+		out_be32((void*)GPIO1_OR,
+			 in_be32((void*)GPIO1_OR) & ~GPIO1_USB_PWR_N);
 
 	for (i=0; i<1000; i++)
 		udelay(1000);

board/korat/config.mk

@@ -24,14 +24,24 @@
 # Korat (PPC440EPx) board
 #
 
-TEXT_BASE = 0xFFFA0000
-
 PLATFORM_CPPFLAGS += -DCONFIG_440=1
 
 ifeq ($(debug),1)
 PLATFORM_CPPFLAGS += -DDEBUG
 endif
 
+ifeq ($(emul),1)
+PLATFORM_CPPFLAGS += -fno-schedule-insns -fno-schedule-insns2
+endif
+
 ifeq ($(dbcr),1)
-PLATFORM_CPPFLAGS += -DCFG_INIT_DBCR=0x8cff0000
+PLATFORM_CPPFLAGS += -DCFG_INIT_DBCR=0x8CFF0000
+endif
+
+ifeq ($(perm),1)
+PLATFORM_CPPFLAGS += -DCONFIG_KORAT_PERMANENT
+TEXT_BASE = 0xFFFA0000
+else
+TEXT_BASE = 0xF7F60000
+LDSCRIPT := $(TOPDIR)/board/$(BOARDDIR)/u-boot-F7FC.lds
 endif

board/korat/init.S

@@ -43,7 +43,7 @@ tlbtab:
 	 * BOOT_CS (FLASH) must be first. Before relocation SA_I can be off to use the
 	 * speed up boot process. It is patched after relocation to enable SA_I
 	 */
-	tlbentry( CFG_BOOT_BASE_ADDR, SZ_256M, CFG_BOOT_BASE_ADDR, 1, AC_R|AC_W|AC_X|SA_G )
+	tlbentry( 0xF0000000, SZ_256M, 0xF0000000, 1, AC_R|AC_W|AC_X|SA_G )
 
 	/*
 	 * TLB entries for SDRAM are not needed on this platform.  They are
@@ -52,24 +52,32 @@ tlbtab:
 
 #ifdef CFG_INIT_RAM_DCACHE
 	/* TLB-entry for init-ram in dcache (SA_I must be turned off!) */
-	tlbentry( CFG_INIT_RAM_ADDR, SZ_64K, CFG_INIT_RAM_ADDR, 0, AC_R|AC_W|AC_X|SA_G )
+	tlbentry( CFG_INIT_RAM_ADDR, SZ_64K, CFG_INIT_RAM_ADDR, 0,
+		  AC_R|AC_W|AC_X|SA_G )
 #endif
 
 	/* TLB-entry for PCI Memory */
-	tlbentry( CFG_PCI_MEMBASE, SZ_256M, CFG_PCI_MEMBASE, 1, AC_R|AC_W|SA_G|SA_I )
-	tlbentry( CFG_PCI_MEMBASE1, SZ_256M, CFG_PCI_MEMBASE1, 1, AC_R|AC_W|SA_G|SA_I )
-	tlbentry( CFG_PCI_MEMBASE2, SZ_256M, CFG_PCI_MEMBASE2, 1, AC_R|AC_W|SA_G|SA_I )
-	tlbentry( CFG_PCI_MEMBASE3, SZ_256M, CFG_PCI_MEMBASE3, 1, AC_R|AC_W|SA_G|SA_I )
+	tlbentry( CFG_PCI_MEMBASE + 0x00000000, SZ_256M,
+		  CFG_PCI_MEMBASE + 0x00000000, 1, AC_R|AC_W|SA_G|SA_I )
+
+	tlbentry( CFG_PCI_MEMBASE + 0x10000000, SZ_256M,
+		  CFG_PCI_MEMBASE + 0x10000000, 1, AC_R|AC_W|SA_G|SA_I )
+
+	tlbentry( CFG_PCI_MEMBASE + 0x20000000, SZ_256M,
+		  CFG_PCI_MEMBASE + 0x20000000, 1, AC_R|AC_W|SA_G|SA_I )
+
+	tlbentry( CFG_PCI_MEMBASE + 0x30000000, SZ_256M,
+		  CFG_PCI_MEMBASE + 0x30000000, 1, AC_R|AC_W|SA_G|SA_I )
 
 	/* TLB-entry for EBC */
 	tlbentry( CFG_CPLD_BASE, SZ_1K, CFG_CPLD_BASE, 1, AC_R|AC_W|SA_G|SA_I )
 
 	/* TLB-entry for Internal Registers & OCM */
 	/* I wonder why this must be executable -- lrj@acm.org 2007-10-08 */
-	tlbentry( 0xE0000000, SZ_16M, 0xE0000000, 0,  AC_R|AC_W|AC_X|SA_I )
+	tlbentry( 0xE0000000, SZ_16M, 0xE0000000, 0, AC_R|AC_W|AC_X|SA_I )
 
 	/*TLB-entry PCI registers*/
-	tlbentry( 0xEEC00000, SZ_1K, 0xEEC00000, 1,  AC_R|AC_W|SA_G|SA_I )
+	tlbentry( 0xEEC00000, SZ_1K, 0xEEC00000, 1, AC_R|AC_W|SA_G|SA_I )
 
 	/* TLB-entry for peripherals */
 	tlbentry( 0xEF000000, SZ_16M, 0xEF000000, 1, AC_R|AC_W|SA_G|SA_I)
@@ -78,3 +86,10 @@ tlbtab:
 	tlbentry(0xE8000000, SZ_64K, 0xE8000000, 1, AC_R|AC_W|SA_G|SA_I)
 
 	tlbtab_end
+
+#if defined(CONFIG_KORAT_PERMANENT)
+	.globl	korat_branch_absolute
+korat_branch_absolute:
+	mtlr	r3
+	blr
+#endif

board/korat/korat.c

@@ -2,12 +2,12 @@
  * (C) Copyright 2007-2008
  * Larry Johnson, lrj@acm.org
  *
- * (C) Copyright 2006-2008
+ * (C) Copyright 2006-2007
  * Stefan Roese, DENX Software Engineering, sr@denx.de.
  *
  * (C) Copyright 2006
  * Jacqueline Pira-Ferriol, AMCC/IBM, jpira-ferriol@fr.ibm.com
- * Alain Saurel,            AMCC/IBM, alain.saurel@fr.ibm.com
+ * Alain Saurel,	    AMCC/IBM, alain.saurel@fr.ibm.com
  *
  * This program is free software; you can redistribute it and/or
  * modify it under the terms of the GNU General Public License as
@@ -39,12 +39,45 @@ extern flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */
 
 ulong flash_get_size(ulong base, int banknum);
 
+#if defined(CONFIG_KORAT_PERMANENT)
+void korat_buzzer(int const on)
+{
+	if (on) {
+		out_8((u8 *) CFG_CPLD_BASE + 0x05,
+		      in_8((u8 *) CFG_CPLD_BASE + 0x05) | 0x80);
+	} else {
+		out_8((u8 *) CFG_CPLD_BASE + 0x05,
+		      in_8((u8 *) CFG_CPLD_BASE + 0x05) & ~0x80);
+	}
+}
+#endif
+
 int board_early_init_f(void)
 {
-	u32 sdr0_pfc1, sdr0_pfc2;
-	u32 reg;
+	uint32_t sdr0_pfc1, sdr0_pfc2;
+	uint32_t reg;
 	int eth;
 
+#if defined(CONFIG_KORAT_PERMANENT)
+	unsigned mscount;
+
+	extern void korat_branch_absolute(uint32_t addr);
+
+	for (mscount = 0;  mscount < CFG_KORAT_MAN_RESET_MS; ++mscount) {
+		udelay(1000);
+		if (gpio_read_in_bit(CFG_GPIO_RESET_PRESSED_)) {
+			/* This call does not return. */
+			korat_branch_absolute(
+				CFG_FLASH1_TOP - 2 * CFG_ENV_SECT_SIZE - 4);
+		}
+	}
+	korat_buzzer(1);
+	while (!gpio_read_in_bit(CFG_GPIO_RESET_PRESSED_))
+		udelay(1000);
+
+	korat_buzzer(0);
+#endif
+
 	mtdcr(ebccfga, xbcfg);
 	mtdcr(ebccfgd, 0xb8400000);
 
@@ -75,8 +108,11 @@ int board_early_init_f(void)
 	mtdcr(uic2vr, 0x00000000);	/* int31 highest, base=0x000 */
 	mtdcr(uic2sr, 0xffffffff);	/* clear all */
 
-	/* take sim card reader and CF controller out of reset */
-	out_8((u8 *) CFG_CPLD_BASE + 0x04, 0x80);
+	/*
+	 * Take sim card reader and CF controller out of reset.  Also enable PHY
+	 * auto-detect until board-specific PHY resets are available.
+	 */
+	out_8((u8 *) CFG_CPLD_BASE + 0x02, 0xC0);
 
 	/* Configure the two Ethernet PHYs.  For each PHY, configure for fiber
 	 * if the SFP module is present, and for copper if it is not present.
@@ -85,8 +121,8 @@ int board_early_init_f(void)
 		if (gpio_read_in_bit(CFG_GPIO_SFP0_PRESENT_ + eth)) {
 			/* SFP module not present: configure PHY for copper. */
 			/* Set PHY to autonegotate 10 MB, 100MB, or 1 GB */
-			out_8((u8 *) CFG_CPLD_BASE + 0x06,
-			      in_8((u8 *) CFG_CPLD_BASE + 0x06) |
+			out_8((u8 *) CFG_CPLD_BASE + 0x03,
+			      in_8((u8 *) CFG_CPLD_BASE + 0x03) |
 			      0x06 << (4 * eth));
 		} else {
 			/* SFP module present: configure PHY for fiber and
@@ -99,10 +135,18 @@ int board_early_init_f(void)
 	gpio_write_bit(CFG_GPIO_PHY0_EN, 1);
 	gpio_write_bit(CFG_GPIO_PHY1_EN, 1);
 
-	/* select Ethernet pins */
+	/* Wait 1 ms, then enable Fiber signal detect to PHYs. */
+	udelay(1000);
+	out_8((u8 *) CFG_CPLD_BASE + 0x03,
+	      in_8((u8 *) CFG_CPLD_BASE + 0x03) | 0x88);
+
+	/* select Ethernet (and optionally IIC1) pins */
 	mfsdr(SDR0_PFC1, sdr0_pfc1);
 	sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_SELECT_MASK) |
 		SDR0_PFC1_SELECT_CONFIG_4;
+#ifdef CONFIG_I2C_MULTI_BUS
+	sdr0_pfc1 |= ((sdr0_pfc1 & ~SDR0_PFC1_SIS_MASK) | SDR0_PFC1_SIS_IIC1_SEL);
+#endif
 	mfsdr(SDR0_PFC2, sdr0_pfc2);
 	sdr0_pfc2 = (sdr0_pfc2 & ~SDR0_PFC2_SELECT_MASK) |
 		SDR0_PFC2_SELECT_CONFIG_4;
@@ -116,6 +160,58 @@ int board_early_init_f(void)
 	return 0;
 }
 
+/*
+ * The boot flash on CS0 normally has its write-enable pin disabled, and so will
+ * not respond to CFI commands.  This routine therefore fills in the flash
+ * information for the boot flash.  (The flash at CS1 operates normally.)
+ */
+ulong board_flash_get_legacy (ulong base, int banknum, flash_info_t * info)
+{
+	uint32_t addr;
+	int i;
+
+	if (1 != banknum)
+		return 0;
+
+	info->size		= CFG_FLASH0_SIZE;
+	info->sector_count	= CFG_FLASH0_SIZE / 0x20000;
+	info->flash_id		= 0x01000000;
+	info->portwidth		= 2;
+	info->chipwidth		= 2;
+	info->buffer_size	= 32;
+	info->erase_blk_tout	= 16384;
+	info->write_tout	= 2;
+	info->buffer_write_tout	= 5;
+	info->vendor		= 2;
+	info->cmd_reset		= 0x00F0;
+	info->interface		= 2;
+	info->legacy_unlock	= 0;
+	info->manufacturer_id	= 1;
+	info->device_id		= 0x007E;
+
+#if CFG_FLASH0_SIZE == 0x01000000
+	info->device_id2	= 0x2101;
+#elif CFG_FLASH0_SIZE == 0x04000000
+	info->device_id2	= 0x2301;
+#else
+#error Unable to set device_id2 for current CFG_FLASH0_SIZE
+#endif
+
+	info->ext_addr		= 0x0040;
+	info->cfi_version	= 0x3133;
+	info->cfi_offset	= 0x0055;
+	info->addr_unlock1	= 0x00000555;
+	info->addr_unlock2	= 0x000002AA;
+	info->name		= "CFI conformant";
+	for (i = 0, addr = -info->size;
+	     i < info->sector_count;
+	     ++i, addr += 0x20000) {
+		info->start[i] = addr;
+		info->protect[i] = 0x00;
+	}
+	return 1;
+}
+
 static int man_data_read(unsigned int addr)
 {
 	/*
@@ -189,12 +285,20 @@ static void set_serial_number(void)
 	 * If the environmental variable "serial#" is not set, try to set it
 	 * from the manufacturer's information serial EEPROM.
 	 */
-	char s[MAN_SERIAL_NO_LENGTH + 1];
+	char s[MAN_INFO_LENGTH + MAN_MAC_ADDR_LENGTH + 2];
+
+	if (getenv("serial#"))
+		return;
+
+	if (!man_data_read_field(s, MAN_INFO_FIELD, MAN_INFO_LENGTH))
+		return;
+
+	s[MAN_INFO_LENGTH] = '-';
+	if (!man_data_read_field(s + MAN_INFO_LENGTH + 1, MAN_MAC_ADDR_FIELD,
+				 MAN_MAC_ADDR_LENGTH))
+		return;
 
-	if (0 == getenv("serial#") &&
-	    0 != man_data_read_field(s, MAN_SERIAL_NO_FIELD,
-				     MAN_SERIAL_NO_LENGTH))
-		setenv("serial#", s);
+	setenv("serial#", s);
 }
 
 static void set_mac_addresses(void)
@@ -204,45 +308,58 @@ static void set_mac_addresses(void)
 	 * set, try to set them from the manufacturer's information serial
 	 * EEPROM.
 	 */
-	char s[MAN_MAC_ADDR_LENGTH + 1];
+
+#if MAN_MAC_ADDR_LENGTH % 2 != 0
+#error MAN_MAC_ADDR_LENGTH must be an even number
+#endif
+
+	char s[(3 * MAN_MAC_ADDR_LENGTH) / 2];
+	char *src;
+	char *dst;
 
 	if (0 != getenv("ethaddr") && 0 != getenv("eth1addr"))
 		return;
 
-	if (0 == man_data_read_field(s, MAN_MAC_ADDR_FIELD,
-				     MAN_MAC_ADDR_LENGTH))
+	if (0 == man_data_read_field(s + (MAN_MAC_ADDR_LENGTH / 2) - 1,
+				     MAN_MAC_ADDR_FIELD, MAN_MAC_ADDR_LENGTH))
 		return;
 
+	for (src = s + (MAN_MAC_ADDR_LENGTH / 2) - 1, dst = s; src != dst;) {
+		*dst++ = *src++;
+		*dst++ = *src++;
+		*dst++ = ':';
+	}
 	if (0 == getenv("ethaddr"))
 		setenv("ethaddr", s);
 
 	if (0 == getenv("eth1addr")) {
-		++s[MAN_MAC_ADDR_LENGTH - 1];
+		++s[((3 * MAN_MAC_ADDR_LENGTH) / 2) - 2];
 		setenv("eth1addr", s);
 	}
 }
 
 int misc_init_r(void)
 {
-	uint pbcr;
-	int size_val = 0;
-	u32 reg;
+	uint32_t pbcr;
+	int size_val;
+	uint32_t reg;
 	unsigned long usb2d0cr = 0;
 	unsigned long usb2phy0cr, usb2h0cr = 0;
 	unsigned long sdr0_pfc1;
-	char *act = getenv("usbact");
-
-	/* Re-do flash sizing to get full correct info */
+	uint32_t const flash1_size = gd->bd->bi_flashsize - CFG_FLASH0_SIZE;
+	char const *const act = getenv("usbact");
 
-	/* adjust flash start and offset */
-	gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize;
+	/*
+	 * Re-do FLASH1 sizing and adjust flash start and offset.
+	 */
+	gd->bd->bi_flashstart = CFG_FLASH1_TOP - flash1_size;
 	gd->bd->bi_flashoffset = 0;
 
-	mtdcr(ebccfga, pb0cr);
+	mtdcr(ebccfga, pb1cr);
 	pbcr = mfdcr(ebccfgd);
-	size_val = ffs(gd->bd->bi_flashsize) - 21;
+	size_val = ffs(flash1_size) - 21;
 	pbcr = (pbcr & 0x0001ffff) | gd->bd->bi_flashstart | (size_val << 17);
-	mtdcr(ebccfga, pb0cr);
+	mtdcr(ebccfga, pb1cr);
 	mtdcr(ebccfgd, pbcr);
 
 	/*
@@ -250,14 +367,37 @@ int misc_init_r(void)
 	 */
 	flash_get_size(gd->bd->bi_flashstart, 0);
 
-	/* Monitor protection ON by default */
-	(void)flash_protect(FLAG_PROTECT_SET, -CFG_MONITOR_LEN, 0xffffffff,
-			    &flash_info[0]);
+	/*
+	 * Re-do FLASH1 sizing and adjust flash offset to reserve space for
+	 * environment
+	 */
+	gd->bd->bi_flashoffset =
+		CFG_ENV_ADDR_REDUND + CFG_ENV_SECT_SIZE - CFG_FLASH1_ADDR;
 
+	mtdcr(ebccfga, pb1cr);
+	pbcr = mfdcr(ebccfgd);
+	size_val = ffs(gd->bd->bi_flashsize - CFG_FLASH0_SIZE) - 21;
+	pbcr = (pbcr & 0x0001ffff) | gd->bd->bi_flashstart | (size_val << 17);
+	mtdcr(ebccfga, pb1cr);
+	mtdcr(ebccfgd, pbcr);
+
+	/* Monitor protection ON by default */
+#if defined(CONFIG_KORAT_PERMANENT)
+	(void)flash_protect(FLAG_PROTECT_SET, CFG_MONITOR_BASE,
+			    CFG_MONITOR_BASE + CFG_MONITOR_LEN - 1,
+			    flash_info + 1);
+#else
+	(void)flash_protect(FLAG_PROTECT_SET, CFG_MONITOR_BASE,
+			    CFG_MONITOR_BASE + CFG_MONITOR_LEN - 1,
+			    flash_info);
+#endif
 	/* Env protection ON by default */
+	(void)flash_protect(FLAG_PROTECT_SET, CFG_ENV_ADDR,
+			    CFG_ENV_ADDR + CFG_ENV_SECT_SIZE - 1,
+			    flash_info);
 	(void)flash_protect(FLAG_PROTECT_SET, CFG_ENV_ADDR_REDUND,
-			    CFG_ENV_ADDR_REDUND + 2 * CFG_ENV_SECT_SIZE - 1,
-			    &flash_info[0]);
+			    CFG_ENV_ADDR_REDUND + CFG_ENV_SECT_SIZE - 1,
+			    flash_info);
 
 	/*
 	 * USB suff...
@@ -393,6 +533,8 @@ int misc_init_r(void)
 
 	set_serial_number();
 	set_mac_addresses();
+	gpio_write_bit(CFG_GPIO_ATMEGA_RESET_, 1);
+
 	return 0;
 }
 
@@ -402,10 +544,10 @@ int checkboard(void)
 	u8 const rev = in_8((u8 *) CFG_CPLD_BASE + 0);
 
 	printf("Board: Korat, Rev. %X", rev);
-	if (s != NULL)
+	if (s)
 		printf(", serial# %s", s);
 
-	printf(", Ethernet PHY 0: ");
+	printf(".\n       Ethernet PHY 0: ");
 	if (gpio_read_out_bit(CFG_GPIO_PHY0_FIBER_SEL))
 		printf("fiber");
 	else
@@ -418,7 +560,10 @@ int checkboard(void)
 		printf("copper");
 
 	printf(".\n");
-	return (0);
+#if defined(CONFIG_KORAT_PERMANENT)
+	printf("       Executing permanent copy of U-Boot.\n");
+#endif
+	return 0;
 }
 
 #if defined(CFG_DRAM_TEST)
@@ -529,23 +674,26 @@ void pci_target_init(struct pci_controller *hose)
 	/*
 	 * PowerPC440EPX PCI Master configuration.
 	 * Map one 1Gig range of PLB/processor addresses to PCI memory space.
-	 * PLB address 0xA0000000-0xDFFFFFFF
-	 *     ==> PCI address 0xA0000000-0xDFFFFFFF
+	 * PLB address 0x80000000-0xBFFFFFFF
+	 *     ==> PCI address 0x80000000-0xBFFFFFFF
 	 * Use byte reversed out routines to handle endianess.
 	 * Make this region non-prefetchable.
 	 */
 	out32r(PCIX0_PMM0MA, 0x00000000);	/* PMM0 Mask/Attribute */
 						/* - disabled b4 setting */
 	out32r(PCIX0_PMM0LA, CFG_PCI_MEMBASE);	/* PMM0 Local Address */
-	out32r(PCIX0_PMM0PCILA, CFG_PCI_MEMBASE); /* PMM0 PCI Low Address */
+	out32r(PCIX0_PMM0PCILA,
+	       CFG_PCI_MEMBASE);		/* PMM0 PCI Low Address */
 	out32r(PCIX0_PMM0PCIHA, 0x00000000);	/* PMM0 PCI High Address */
 	out32r(PCIX0_PMM0MA, 0xE0000001);	/* 512M + No prefetching, */
 						/* and enable region */
 
 	out32r(PCIX0_PMM1MA, 0x00000000);	/* PMM0 Mask/Attribute */
 						/* - disabled b4 setting */
-	out32r(PCIX0_PMM1LA, CFG_PCI_MEMBASE2); /* PMM0 Local Address */
-	out32r(PCIX0_PMM1PCILA, CFG_PCI_MEMBASE2); /* PMM0 PCI Low Address */
+	out32r(PCIX0_PMM1LA,
+	       CFG_PCI_MEMBASE + 0x20000000);	/* PMM0 Local Address */
+	out32r(PCIX0_PMM1PCILA,
+	       CFG_PCI_MEMBASE + 0x20000000);	/* PMM0 PCI Low Address */
 	out32r(PCIX0_PMM1PCIHA, 0x00000000);	/* PMM0 PCI High Address */
 	out32r(PCIX0_PMM1MA, 0xE0000001);	/* 512M + No prefetching, */
 						/* and enable region */

board/korat/u-boot-F7FC.lds

@@ -0,0 +1,143 @@
+/*
+ * (C) Copyright 2002
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  .resetvec 0xF7FBFFFC :
+  {
+    *(.resetvec)
+  } = 0xffff
+
+  .bootpg 0xF7FBF000 :
+  {
+    cpu/ppc4xx/start.o	(.bootpg)
+  } = 0xffff
+
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)		}
+  .rela.text     : { *(.rela.text) 	}
+  .rel.data      : { *(.rel.data)		}
+  .rela.data     : { *(.rela.data) 	}
+  .rel.rodata    : { *(.rel.rodata) 	}
+  .rela.rodata   : { *(.rela.rodata) 	}
+  .rel.got       : { *(.rel.got)		}
+  .rela.got      : { *(.rela.got)		}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)		}
+  .rela.bss      : { *(.rela.bss)		}
+  .rel.plt       : { *(.rel.plt)		}
+  .rela.plt      : { *(.rela.plt)		}
+  .init          : { *(.init)	}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    /* WARNING - the following is hand-optimized to fit within	*/
+    /* the sector layout of our flash chips!	XXX FIXME XXX	*/
+
+    cpu/ppc4xx/start.o	(.text)
+
+    *(.text)
+    *(.fixup)
+    *(.got1)
+  }
+  _etext = .;
+  PROVIDE (etext = .);
+  .rodata    :
+  {
+    *(.rodata)
+    *(.rodata1)
+    *(.rodata.str1.4)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x00FF) & 0xFFFFFF00;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  . = .;
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  . = .;
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(256);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(256);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss (NOLOAD)       :
+  {
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+  }
+
+  _end = . ;
+  PROVIDE (end = .);
+}

board/lwmon5/sdram.c

@@ -6,7 +6,7 @@
  * Alain Saurel,	    AMCC/IBM, alain.saurel@fr.ibm.com
  * Robert Snyder,	    AMCC/IBM, rob.snyder@fr.ibm.com
  *
- * (C) Copyright 2007
+ * (C) Copyright 2007-2008
  * Stefan Roese, DENX Software Engineering, sr@denx.de.
  *
  * This program is free software; you can redistribute it and/or
@@ -35,6 +35,7 @@
 #include <asm/mmu.h>
 #include <asm/io.h>
 #include <ppc440.h>
+#include <watchdog.h>
 
 /*
  * This DDR2 setup code can dynamically setup the TLB entries for the DDR2 memory
@@ -99,87 +100,37 @@ static void wait_ddr_idle(void)
 	 */
 }
 
-static void blank_string(int size)
-{
-	int i;
-
-	for (i=0; i<size; i++)
-		putc('\b');
-	for (i=0; i<size; i++)
-		putc(' ');
-	for (i=0; i<size; i++)
-		putc('\b');
-}
-
 static void program_ecc(u32 start_address,
 			u32 num_bytes,
 			u32 tlb_word2_i_value)
 {
-	u32 current_address;
-	u32 end_address;
-	u32 address_increment;
 	u32 val;
-	char str[] = "ECC generation -";
-	char slash[] = "\\|/-\\|/-";
-	int loop = 0;
-	int loopi = 0;
-
-	current_address = start_address;
+	u32 current_addr = start_address;
+	int bytes_remaining;
 
 	sync();
-	eieio();
 	wait_ddr_idle();
 
-	if (tlb_word2_i_value == TLB_WORD2_I_ENABLE) {
-		/* ECC bit set method for non-cached memory */
-		address_increment = 4;
-		end_address = current_address + num_bytes;
-
-		puts(str);
-
-		while (current_address < end_address) {
-			*((u32 *)current_address) = 0x00000000;
-			current_address += address_increment;
-
-			if ((loop++ % (2 << 20)) == 0) {
-				putc('\b');
-				putc(slash[loopi++ % 8]);
-			}
-		}
+	/*
+	 * Because of 440EPx errata CHIP 11, we don't touch the last 256
+	 * bytes of SDRAM.
+	 */
+	bytes_remaining = num_bytes - CFG_MEM_TOP_HIDE;
 
-		blank_string(strlen(str));
-	} else {
-		/* ECC bit set method for cached memory */
-#if 0 /* test-only: will remove this define later, when ECC problems are solved! */
-		/*
-		 * Some boards (like lwmon5) need to preserve the memory
-		 * content upon ECC generation (for the log-buffer).
-		 * Therefore we don't fill the memory with a pattern or
-		 * just zero it, but write the same values back that are
-		 * already in the memory cells.
-		 */
-		address_increment = CFG_CACHELINE_SIZE;
-		end_address = current_address + num_bytes;
-
-		current_address = start_address;
-		while (current_address < end_address) {
-			/*
-			 * TODO: Th following sequence doesn't work correctly.
-			 * Just invalidating and flushing the cache doesn't
-			 * seem to trigger the re-write of the memory.
-			 */
-			ppcDcbi(current_address);
-			ppcDcbf(current_address);
-			current_address += CFG_CACHELINE_SIZE;
-		}
-#else
-		dcbz_area(start_address, num_bytes);
-		dflush();
-#endif
+	/*
+	 * We have to write the ECC bytes by zeroing and flushing in smaller
+	 * steps, since the whole 256MByte takes too long for the external
+	 * watchdog.
+	 */
+	while (bytes_remaining > 0) {
+		dcbz_area(current_addr, min((64 << 20), bytes_remaining));
+		current_addr += 64 << 20;
+		bytes_remaining -= 64 << 20;
+		WATCHDOG_RESET();
 	}
+	dflush();
 
 	sync();
-	eieio();
 	wait_ddr_idle();
 
 	/* Clear error status */
@@ -191,7 +142,6 @@ static void program_ecc(u32 start_address,
 	mtsdram(DDR0_01, ((val &~ DDR0_01_INT_MASK_MASK) | DDR0_01_INT_MASK_ALL_OFF));
 
 	sync();
-	eieio();
 	wait_ddr_idle();
 }
 #endif

board/prodrive/alpr/alpr.c

@@ -23,10 +23,12 @@
 
 
 #include <common.h>
-#include <asm/processor.h>
+#include <libfdt.h>
+#include <fdt_support.h>
 #include <spd_sdram.h>
 #include <ppc4xx_enet.h>
 #include <miiphy.h>
+#include <asm/processor.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -315,3 +317,24 @@ int post_hotkeys_pressed(void)
 	return (ctrlc());
 }
 #endif
+
+#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
+void ft_board_setup(void *blob, bd_t *bd)
+{
+	u32 val[4];
+	int rc;
+
+	ft_cpu_setup(blob, bd);
+
+	/* Fixup NOR mapping */
+	val[0] = 0;				/* chip select number */
+	val[1] = 0;				/* always 0 */
+	val[2] = gd->bd->bi_flashstart;
+	val[3] = gd->bd->bi_flashsize;
+	rc = fdt_find_and_setprop(blob, "/plb/opb/ebc", "ranges",
+				  val, sizeof(val), 1);
+	if (rc)
+		printf("Unable to update property NOR mapping, err=%s\n",
+		       fdt_strerror(rc));
+}
+#endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */

board/prodrive/alpr/init.S

@@ -90,7 +90,16 @@ tlbtab:
 	tlbentry( CFG_PERIPHERAL_BASE, SZ_256M, 0x40000000, 1, AC_R|AC_W|SA_G|SA_I )
 	tlbentry( CFG_ISRAM_BASE, SZ_4K, 0x80000000, 0, AC_R|AC_W|AC_X )
 	tlbentry( CFG_ISRAM_BASE + 0x1000, SZ_4K, 0x80001000, 0, AC_R|AC_W|AC_X )
+#ifdef CONFIG_4xx_DCACHE
+	tlbentry( CFG_SDRAM_BASE, SZ_256M, 0x00000000, 0, AC_R|AC_W|AC_X|SA_G)
+#else
 	tlbentry( CFG_SDRAM_BASE, SZ_256M, 0x00000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I )
+#endif
+
+#ifdef CFG_INIT_RAM_DCACHE
+	/* TLB-entry for init-ram in dcache (SA_I must be turned off!) */
+	tlbentry( CFG_INIT_RAM_ADDR, SZ_64K, CFG_INIT_RAM_ADDR, 0, AC_R|AC_W|AC_X|SA_G )
+#endif
 	tlbentry( CFG_PCI_BASE, SZ_256M, 0x00000000, 2, AC_R|AC_W|SA_G|SA_I )
 
 	/* PCI */

cpu/ppc4xx/4xx_enet.c

@@ -274,7 +274,7 @@ static void emac_loopback_disable(EMAC_4XX_HW_PST hw_p)
 static void ppc_4xx_eth_halt (struct eth_device *dev)
 {
 	EMAC_4XX_HW_PST hw_p = dev->priv;
-	uint32_t failsafe = 10000;
+	u32 val = 10000;
 
 	out_be32((void *)EMAC_IER + hw_p->hw_addr, 0x00000000);	/* disable emac interrupts */
 
@@ -290,8 +290,8 @@ static void ppc_4xx_eth_halt (struct eth_device *dev)
 	/* wait for reset */
 	while (mfdcr (malrxcasr) & (MAL_CR_MMSR >> hw_p->devnum)) {
 		udelay (1000);	/* Delay 1 MS so as not to hammer the register */
-		failsafe--;
-		if (failsafe == 0)
+		val--;
+		if (val == 0)
 			break;
 	}
 
@@ -308,6 +308,13 @@ static void ppc_4xx_eth_halt (struct eth_device *dev)
 	hw_p->print_speed = 1;	/* print speed message again next time */
 #endif
 
+#if defined(CONFIG_460EX) || defined(CONFIG_460GT)
+	/* don't bypass the TAHOE0/TAHOE1 cores for Linux */
+	mfsdr(SDR0_ETH_CFG, val);
+	val &= ~(SDR0_ETH_CFG_TAHOE0_BYPASS | SDR0_ETH_CFG_TAHOE1_BYPASS);
+	mtsdr(SDR0_ETH_CFG, val);
+#endif
+
 	return;
 }
 
@@ -494,11 +501,18 @@ int ppc_4xx_eth_setup_bridge(int devnum, bd_t * bis)
 	u32 zmiifer;		/* ZMII0_FER reg. */
 	u32 rmiifer;		/* RGMII0_FER reg. Bridge 0 */
 	u32 rmiifer1;		/* RGMII0_FER reg. Bridge 1 */
+	int mode;
 
 	zmiifer  = 0;
 	rmiifer  = 0;
 	rmiifer1 = 0;
 
+#if defined(CONFIG_460EX)
+	mode = 9;
+#else
+	mode = 10;
+#endif
+
 	/* TODO:
 	 * NOTE: 460GT has 2 RGMII bridge cores:
 	 *		emac0 ------ RGMII0_BASE
@@ -520,7 +534,7 @@ int ppc_4xx_eth_setup_bridge(int devnum, bd_t * bis)
 	 * Right now only 2*RGMII is supported. Please extend when needed.
 	 * sr - 2008-02-19
 	 */
-	switch (9) {
+	switch (mode) {
 	case 1:
 		/* 1 MII - 460EX */
 		/* GMC0 EMAC4_0, ZMII Bridge */
@@ -703,6 +717,11 @@ static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis)
 #ifdef CONFIG_4xx_DCACHE
 	static u32 last_used_ea = 0;
 #endif
+#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
+    defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
+    defined(CONFIG_405EX)
+	int rgmii_channel;
+#endif
 
 	EMAC_4XX_HW_PST hw_p = dev->priv;
 
@@ -836,10 +855,12 @@ static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis)
 		reg = CONFIG_PHY1_ADDR;
 		break;
 #endif
-#if defined (CONFIG_440GX)
+#if defined (CONFIG_PHY2_ADDR)
 	case 2:
 		reg = CONFIG_PHY2_ADDR;
 		break;
+#endif
+#if defined (CONFIG_PHY3_ADDR)
 	case 3:
 		reg = CONFIG_PHY3_ADDR;
 		break;
@@ -1006,12 +1027,17 @@ static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis)
 #if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
     defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
     defined(CONFIG_405EX)
+	if (devnum >= 2)
+		rgmii_channel = devnum - 2;
+	else
+		rgmii_channel = devnum;
+
 	if (speed == 1000)
-		reg = (RGMII_SSR_SP_1000MBPS << RGMII_SSR_V (devnum));
+		reg = (RGMII_SSR_SP_1000MBPS << RGMII_SSR_V(rgmii_channel));
 	else if (speed == 100)
-		reg = (RGMII_SSR_SP_100MBPS << RGMII_SSR_V (devnum));
+		reg = (RGMII_SSR_SP_100MBPS << RGMII_SSR_V(rgmii_channel));
 	else if (speed == 10)
-		reg = (RGMII_SSR_SP_10MBPS << RGMII_SSR_V (devnum));
+		reg = (RGMII_SSR_SP_10MBPS << RGMII_SSR_V(rgmii_channel));
 	else {
 		printf("Error in RGMII Speed\n");
 		return -1;
@@ -1131,7 +1157,7 @@ static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis)
 #endif
 
 #if defined(CONFIG_460EX) || defined(CONFIG_460GT)
-		mtdcr (malrxctp8r, hw_p->rx);
+		mtdcr (malrxctp8r, hw_p->rx_phys);
 		/* set RX buffer size */
 		mtdcr (malrcbs8, ENET_MAX_MTU_ALIGNED / 16);
 #else
@@ -1160,6 +1186,26 @@ static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis)
 		mtdcr (malrcbs3, ENET_MAX_MTU_ALIGNED / 16);
 		break;
 #endif /* CONFIG_440GX */
+#if defined (CONFIG_460GT)
+	case 2:
+		/* setup MAL tx & rx channel pointers */
+		mtdcr (maltxbattr, 0x0);
+		mtdcr (malrxbattr, 0x0);
+		mtdcr (maltxctp2r, hw_p->tx_phys);
+		mtdcr (malrxctp16r, hw_p->rx_phys);
+		/* set RX buffer size */
+		mtdcr (malrcbs16, ENET_MAX_MTU_ALIGNED / 16);
+		break;
+	case 3:
+		/* setup MAL tx & rx channel pointers */
+		mtdcr (maltxbattr, 0x0);
+		mtdcr (malrxbattr, 0x0);
+		mtdcr (maltxctp3r, hw_p->tx_phys);
+		mtdcr (malrxctp24r, hw_p->rx_phys);
+		/* set RX buffer size */
+		mtdcr (malrcbs24, ENET_MAX_MTU_ALIGNED / 16);
+		break;
+#endif /* CONFIG_460GT */
 	case 0:
 	default:
 		/* setup MAL tx & rx channel pointers */
@@ -1866,14 +1912,22 @@ int ppc_4xx_eth_initialize (bd_t * bis)
 		case 2:
 			memcpy(ethaddr[eth_num + CONFIG_EMAC_NR_START],
 			       bis->bi_enet2addr, 6);
+#if defined(CONFIG_460GT)
+			hw_addr[eth_num] = 0x300;
+#else
 			hw_addr[eth_num] = 0x400;
+#endif
 			break;
 #endif
 #ifdef CONFIG_HAS_ETH3
 		case 3:
 			memcpy(ethaddr[eth_num + CONFIG_EMAC_NR_START],
 			       bis->bi_enet3addr, 6);
+#if defined(CONFIG_460GT)
+			hw_addr[eth_num] = 0x400;
+#else
 			hw_addr[eth_num] = 0x600;
+#endif
 			break;
 #endif
 		}

cpu/ppc4xx/cpu_init.c

@@ -99,10 +99,107 @@ DECLARE_GLOBAL_DATA_PTR;
 # endif
 #endif /* CFG_INIT_DCACHE_CS */
 
+#ifndef CFG_PLL_RECONFIG
+#define CFG_PLL_RECONFIG	0
+#endif
+
+void reconfigure_pll(u32 new_cpu_freq)
+{
+#if defined(CONFIG_440EPX)
+	int	reset_needed = 0;
+	u32	reg, temp;
+	u32	prbdv0, target_prbdv0,				/* CLK_PRIMBD */
+		fwdva, target_fwdva, fwdvb, target_fwdvb,	/* CLK_PLLD */
+		fbdv, target_fbdv, lfbdv, target_lfbdv,
+		perdv0,	target_perdv0,				/* CLK_PERD */
+		spcid0,	target_spcid0;				/* CLK_SPCID */
+
+	/* Reconfigure clocks if necessary.
+	 * See PPC440EPx User's Manual, sections 8.2 and 14 */
+	if (new_cpu_freq == 667) {
+		target_prbdv0 = 2;
+		target_fwdva = 2;
+		target_fwdvb = 4;
+		target_fbdv = 20;
+		target_lfbdv = 1;
+		target_perdv0 = 4;
+		target_spcid0 = 4;
+
+		mfcpr(clk_primbd, reg);
+		temp = (reg & PRBDV_MASK) >> 24;
+		prbdv0 = temp ? temp : 8;
+		if (prbdv0 != target_prbdv0) {
+			reg &= ~PRBDV_MASK;
+			reg |= ((target_prbdv0 == 8 ? 0 : target_prbdv0) << 24);
+			mtcpr(clk_primbd, reg);
+			reset_needed = 1;
+		}
+
+		mfcpr(clk_plld, reg);
+
+		temp = (reg & PLLD_FWDVA_MASK) >> 16;
+		fwdva = temp ? temp : 16;
+
+		temp = (reg & PLLD_FWDVB_MASK) >> 8;
+		fwdvb = temp ? temp : 8;
+
+		temp = (reg & PLLD_FBDV_MASK) >> 24;
+		fbdv = temp ? temp : 32;
+
+		temp = (reg & PLLD_LFBDV_MASK);
+		lfbdv = temp ? temp : 64;
+
+		if (fwdva != target_fwdva || fbdv != target_fbdv || lfbdv != target_lfbdv) {
+			reg &= ~(PLLD_FWDVA_MASK | PLLD_FWDVB_MASK |
+				 PLLD_FBDV_MASK | PLLD_LFBDV_MASK);
+			reg |= ((target_fwdva == 16 ? 0 : target_fwdva) << 16) |
+				((target_fwdvb == 8 ? 0 : target_fwdvb) << 8) |
+				((target_fbdv == 32 ? 0 : target_fbdv) << 24) |
+				(target_lfbdv == 64 ? 0 : target_lfbdv);
+			mtcpr(clk_plld, reg);
+			reset_needed = 1;
+		}
+
+		mfcpr(clk_perd, reg);
+		perdv0 = (reg & CPR0_PERD_PERDV0_MASK) >> 24;
+		if (perdv0 != target_perdv0) {
+			reg &= ~CPR0_PERD_PERDV0_MASK;
+			reg |= (target_perdv0 << 24);
+			mtcpr(clk_perd, reg);
+			reset_needed = 1;
+		}
+
+		mfcpr(clk_spcid, reg);
+		temp = (reg & CPR0_SPCID_SPCIDV0_MASK) >> 24;
+		spcid0 = temp ? temp : 4;
+		if (spcid0 != target_spcid0) {
+			reg &= ~CPR0_SPCID_SPCIDV0_MASK;
+			reg |= ((target_spcid0 == 4 ? 0 : target_spcid0) << 24);
+			mtcpr(clk_spcid, reg);
+			reset_needed = 1;
+		}
+
+		/* Set reload inhibit so configuration will persist across
+		 * processor resets */
+		mfcpr(clk_icfg, reg);
+		reg &= ~CPR0_ICFG_RLI_MASK;
+		reg |= 1 << 31;
+		mtcpr(clk_icfg, reg);
+	}
+
+	/* Reset processor if configuration changed */
+	if (reset_needed) {
+		__asm__ __volatile__ ("sync; isync");
+		mtspr(dbcr0, 0x20000000);
+	}
+#endif
+}
+
 /*
  * Breath some life into the CPU...
  *
- * Set up the memory map,
+ * Reconfigure PLL if necessary,
+ * set up the memory map,
  * initialize a bunch of registers
  */
 void
@@ -111,6 +208,7 @@ cpu_init_f (void)
 #if defined(CONFIG_WATCHDOG)
 	unsigned long val;
 #endif
+	reconfigure_pll(CFG_PLL_RECONFIG);
 
 #if (defined(CONFIG_405EP) || defined (CONFIG_405EX)) && !defined(CFG_4xx_GPIO_TABLE)
 	/*
@@ -135,6 +233,7 @@ cpu_init_f (void)
 #if defined (CFG_GPIO0_TCR)
 	out32(GPIO0_TCR, CFG_GPIO0_TCR);	/* enable output driver for outputs	*/
 #endif
+#endif /* CONFIG_405EP ... && !CFG_4xx_GPIO_TABLE */
 
 #if defined (CONFIG_405EP)
 	/*
@@ -147,7 +246,6 @@ cpu_init_f (void)
 	 */
 	mtdcr(cpc0_pci, mfdcr(cpc0_pci) | CPC0_PCI_HOST_CFG_EN | CPC0_PCI_ARBIT_EN);
 #endif /* CONFIG_405EP */
-#endif /* CONFIG_405EP */
 
 #if defined(CFG_4xx_GPIO_TABLE)
 	gpio_set_chip_configuration();

cpu/ppc4xx/denali_spd_ddr2.c

@@ -1093,10 +1093,10 @@ long int initdram(int board_type)
 
 	program_ddr0_06(dimm_ranks, iic0_dimm_addr, num_dimm_banks, sdram_freq);
 
-	/*------------------------------------------------------------------
+	/*
 	 * TODO: tFAW not found in SPD.  Value of 13 taken from Sequoia
-	 * board SDRAM, but may be overly concervate.
-	 *-----------------------------------------------------------------*/
+	 * board SDRAM, but may be overly conservative.
+	 */
 	mtsdram(DDR0_07, DDR0_07_NO_CMD_INIT_ENCODE(0) |
 		DDR0_07_TFAW_ENCODE(13) |
 		DDR0_07_AUTO_REFRESH_MODE_ENCODE(1) |
@@ -1181,26 +1181,29 @@ long int initdram(int board_type)
 	denali_wait_for_dlllock();
 
 #if defined(CONFIG_DDR_DATA_EYE)
-	/* -----------------------------------------------------------+
-	 * Perform data eye search if requested.
-	 * ----------------------------------------------------------*/
-	program_tlb(0, CFG_SDRAM_BASE, dram_size, TLB_WORD2_I_ENABLE);
+	/*
+	 * Map the first 1 MiB of memory in the TLB, and perform the data eye
+	 * search.
+	 */
+	program_tlb(0, CFG_SDRAM_BASE, TLB_1MB_SIZE, TLB_WORD2_I_ENABLE);
 	denali_core_search_data_eye();
 	denali_sdram_register_dump();
-	remove_tlb(CFG_SDRAM_BASE, dram_size);
+	remove_tlb(CFG_SDRAM_BASE, TLB_1MB_SIZE);
 #endif
 
 #if defined(CONFIG_ZERO_SDRAM) || defined(CONFIG_DDR_ECC)
 	program_tlb(0, CFG_SDRAM_BASE, dram_size, 0);
 	sync();
-	eieio();
 	/* Zero the memory */
 	debug("Zeroing SDRAM...");
-	dcbz_area(CFG_SDRAM_BASE, dram_size);
+#if defined(CFG_MEM_TOP_HIDE)
+	dcbz_area(CFG_SDRAM_BASE, dram_size - CFG_MEM_TOP_HIDE);
+#else
+#error Please define CFG_MEM_TOP_HIDE (see README) in your board config file
+#endif
 	dflush();
 	debug("Completed\n");
 	sync();
-	eieio();
 	remove_tlb(CFG_SDRAM_BASE, dram_size);
 
 #if defined(CONFIG_DDR_ECC)
@@ -1211,7 +1214,6 @@ long int initdram(int board_type)
 		u32 val;
 
 		sync();
-		eieio();
 		/* Clear error status */
 		mfsdram(DDR0_00, val);
 		mtsdram(DDR0_00, val | DDR0_00_INT_ACK_ALL);
@@ -1229,7 +1231,6 @@ long int initdram(int board_type)
 		print_mcsr();
 #endif
 		sync();
-		eieio();
 	}
 #endif /* defined(CONFIG_DDR_ECC) */
 #endif /* defined(CONFIG_ZERO_SDRAM) || defined(CONFIG_DDR_ECC) */

cpu/ppc4xx/interrupts.c

@@ -218,15 +218,16 @@ static void uic_interrupt(u32 uic_base, int vec_base)
 			} else {
 				set_dcr(uic_base + UIC_ER,
 					get_dcr(uic_base + UIC_ER) &
-					~(0x80000000 >> vec));
+					~(0x80000000 >> (vec & 0x1f)));
 				printf("Masking bogus interrupt vector %d"
 				       " (UIC_BASE=0x%x)\n", vec, uic_base);
 			}
 
 			/*
-			 * After servicing the interrupt, we have to remove the status indicator.
+			 * After servicing the interrupt, we have to remove the
+			 * status indicator
 			 */
-			set_dcr(uic_base + UIC_SR, (0x80000000 >> vec));
+			set_dcr(uic_base + UIC_SR, (0x80000000 >> (vec & 0x1f)));
 		}
 
 		/*

doc/README.korat

@@ -0,0 +1,51 @@
+The Korat board has two NOR flashes, FLASH0 and FLASH1, which are connected to
+chip select 0 and 1, respectively.  FLASH0 contains 16 MiB, and is mapped to
+addresses 0xFF000000 - 0xFFFFFFFF as U-Boot Flash Bank #2.  FLASH1 contains
+from 16 to 128 MiB, and is mapped to 0xF?000000 - 0xF7FFFFFF as U-Boot Flash
+Bank #1 (with the starting address depending on the flash size detected at
+runtime).  The write-enable pin on FLASH0 is disabled, so the contents of FLASH0
+cannot be modified in the field.  This also prevents FLASH0 from executing
+commands to return chip information, so its configuration is hard-coded in
+U-Boot.
+
+There are two versions of U-Boot for Korat: "permanent" and "upgradable".  The
+permanent U-Boot is pre-programmed at the top of FLASH0, e.g., at addresses
+0xFFFA0000 - 0xFFFFFFFF for the current 384 KiB size.  The upgradable U-Boot is
+located 256 KiB from the top of FLASH1, e.g. at addresses 0xF7F6000 - 0xF7FC0000
+for the current 384 KiB size.  FLASH1 addresses 0xF7FE0000 - 0xF7FF0000 are
+used for the U-Boot environmental parameters, and addresses 0xF7FC0000 -
+0xF7FDFFFF are used for the redundant copy of the parameters.  These locations
+are used by both versions of U-Boot.
+
+On booting, the permanent U-Boot in FLASH0 begins executing.  After performing
+minimal setup, it monitors the state of the board's Reset switch (GPIO47).  If
+the switch is sensed as open before a timeout period, then U-Boot branches to
+address 0xF7FBFFFC.  This causes the upgradable U-Boot to execute from the
+beginning.  If the switch remains closed thoughout the timeout period, the
+permanent U-Boot activates the on-board buzzer until the switch is sensed as
+opened.  It then continues to execute without branching to FLASH1.  The effect
+of this is that normally the Korat board boots its upgradable U-Boot, but, if
+this has been corrupted, the user can boot the permanent U-Boot, which can then
+be used to erase and reload FLASH1 as needed.
+
+Note that it is not necessary for the permanent U-Boot to have all the latest
+features, but only that it have sufficient functionality (working "tftp",
+"erase", "cp.b", etc.) to repair FLASH1.  Also, the permanent U-Boot makes no
+assumptions about the size of FLASH1 or the size of the upgradable U-Boot: it is
+sufficient that the upgradable U-Boot can be started by a branch to 0xF7FBFFFC.
+
+The build sequence:
+
+	make korat_config
+	make all perm=1
+
+builds the permanent U-Boot by selecting loader file "u-boot.lds" and defining
+preprocessor symbol "CONFIG_KORAT_PERMANENT".  The default build:
+
+	make korat_config
+	make all
+
+creates the upgradable U-Boot but selecting loader file "u-boot-F7FC.lds" and
+leaving preprocessor symbol "CONFIG_KORAT_PERMANENT" undefined.
+
+2008-02-22, Larry Johnson <lrj@acm.org>

include/configs/DU440.h

@@ -157,10 +157,9 @@
  */
 #define CFG_MBYTES_SDRAM        (1024)	/* 512 MiB      TODO: remove    */
 #define CONFIG_DDR_DATA_EYE		/* use DDR2 optimization        */
+#define CFG_MEM_TOP_HIDE        (4 << 10) /* don't use last 4kbytes     */
+					/* 440EPx errata CHIP 11        */
 #define CONFIG_SPD_EEPROM		/* Use SPD EEPROM for setup     */
-#if 0
-#define CONFIG_ZERO_SDRAM		/* Zero SDRAM after setup       */
-#endif
 #define CONFIG_DDR_ECC			/* Use ECC when available       */
 #define SPD_EEPROM_ADDRESS	{0x50}
 #define CONFIG_PROG_SDRAM_TLB
@@ -244,9 +243,6 @@
 	"update=protect off FFFA0000 FFFFFFFF;era FFFA0000 FFFFFFFF;"	\
 		"cp.b 100000 FFFA0000 60000\0"				\
 	""
-#if 0
-#define CONFIG_BOOTCOMMAND	"run flash_self"
-#endif
 
 #define CONFIG_PREBOOT                  /* enable preboot variable      */
 
@@ -264,7 +260,7 @@ int du440_phy_addr(int devnum);
 #define CONFIG_PHY_ADDR		du440_phy_addr(0) /* PHY address	*/
 
 #define CONFIG_PHY_RESET        1	/* reset phy upon startup	*/
-#define CONFIG_PHY_GIGE		1	/* Include GbE detection	*/
+#undef CONFIG_PHY_GIGE			/* no GbE detection		*/
 
 #define CONFIG_HAS_ETH0
 #define CFG_RX_ETH_BUFFER	128
@@ -295,7 +291,9 @@ int du440_phy_addr(int devnum);
 
 #include <config_cmd_default.h>
 
+#define CONFIG_CMD_AUTOSCRIPT
 #define CONFIG_CMD_BSP
+#define CONFIG_CMD_BMP
 #define CONFIG_CMD_DATE
 #define CONFIG_CMD_ASKENV
 #define CONFIG_CMD_DHCP
@@ -431,8 +429,6 @@ int du440_phy_addr(int devnum);
 #define CONFIG_KGDB_SER_INDEX	2	/* which serial port to use */
 #endif
 
-#if 0
-#define CONFIG_SHOW_ACTIVITY      1
-#endif
+#define CONFIG_AUTOSCRIPT	1
 
 #endif	/* __CONFIG_H */

include/configs/alpr.h

@@ -1,5 +1,5 @@
 /*
- * (C) Copyright 2006-2007
+ * (C) Copyright 2006-2008
  * Stefan Roese, DENX Software Engineering, sr@denx.de.
  *
  * See file CREDITS for list of people who contributed to this
@@ -35,6 +35,7 @@
 #define CONFIG_LAST_STAGE_INIT	1	    /* call last_stage_init()	*/
 #undef	CFG_DRAM_TEST			    /* Disable-takes long time! */
 #define CONFIG_SYS_CLK_FREQ	33333333    /* external freq to pll	*/
+#define CONFIG_4xx_DCACHE		/* Enable i- and d-cache	*/
 
 /*-----------------------------------------------------------------------
  * Base addresses -- Note these are effective addresses where the
@@ -144,6 +145,8 @@
 #define	CONFIG_EXTRA_ENV_SETTINGS					\
 	"netdev=eth3\0"							\
 	"hostname=alpr\0"						\
+	"fdt_file=alpr/alpr.dtb\0"					\
+	"fdt_addr=400000\0"						\
 	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
 		"nfsroot=${serverip}:${rootpath} ${init}\0"		\
 	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
@@ -158,6 +161,10 @@
 		"bootm ${kernel_addr} ${ramdisk_addr}\0"		\
 	"net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;"     \
 	        "bootm\0"						\
+	"net_nfs_fdt=tftp 200000 ${bootfile};"				\
+		"tftp ${fdt_addr} ${fdt_file};"				\
+		"run nfsargs addip addtty;"				\
+		"bootm 200000 - ${fdt_addr}\0"				\
 	"rootpath=/opt/projects/alpr/nfs_root\0"			\
 	"bootfile=/alpr/uImage\0"					\
 	"kernel_addr=fff00000\0"					\
@@ -370,4 +377,9 @@
 #define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port */
 #define CONFIG_KGDB_SER_INDEX	2	/* which serial port to use */
 #endif
+
+/* pass open firmware flat tree */
+#define CONFIG_OF_LIBFDT	1
+#define CONFIG_OF_BOARD_SETUP	1
+
 #endif	/* __CONFIG_H */

include/configs/canyonlands.h

@@ -27,16 +27,21 @@
 /*-----------------------------------------------------------------------
  * High Level Configuration Options
  *----------------------------------------------------------------------*/
-#define CONFIG_CANYONLANDS	1	/* Board is Canyonlands	*/
+/* This config file is used for Canyonlands (460EX) and Glacier (460GT)	*/
+#ifndef CONFIG_CANYONLANDS
+#define CONFIG_460GT		1	/* Specific PPC460GT		*/
+#else
+#define CONFIG_460EX		1	/* Specific PPC460EX		*/
+#endif
 #define CONFIG_440		1
 #define CONFIG_4xx		1	/* ... PPC4xx family */
-#define CONFIG_460EX		1	/* Specific PPC460EX support */
 
 #define CONFIG_SYS_CLK_FREQ	66666667	/* external freq to pll	*/
 
 #define CONFIG_BOARD_EARLY_INIT_F	1	/* Call board_early_init_f */
 #define CONFIG_BOARD_EARLY_INIT_R	1	/* Call board_early_init_r */
 #define CONFIG_MISC_INIT_R		1	/* Call misc_init_r */
+#define CONFIG_BOARD_TYPES		1	/* support board types */
 
 /*-----------------------------------------------------------------------
  * Base addresses -- Note these are effective addresses where the
@@ -262,8 +267,15 @@
 #define CONFIG_MII		1	/* MII PHY management		*/
 #define CONFIG_PHY_ADDR		0	/* PHY address, See schematics	*/
 #define CONFIG_PHY1_ADDR	1
-#define CONFIG_HAS_ETH0		1
-#define CONFIG_HAS_ETH1		1	/* add support for "eth1addr"   */
+#define CONFIG_HAS_ETH0
+#define CONFIG_HAS_ETH1
+/* Only Glacier (460GT) has 4 EMAC interfaces */
+#ifdef CONFIG_460GT
+#define CONFIG_PHY2_ADDR	2
+#define CONFIG_PHY3_ADDR	3
+#define CONFIG_HAS_ETH2
+#define CONFIG_HAS_ETH3
+#endif
 #define CONFIG_NET_MULTI	1
 
 #define CONFIG_PHY_RESET	1	/* reset phy upon startup	*/
@@ -275,6 +287,8 @@
 /*-----------------------------------------------------------------------
  * USB-OHCI
  *----------------------------------------------------------------------*/
+/* Only Canyonlands (460EX) has USB */
+#ifdef CONFIG_460EX
 #define CONFIG_USB_OHCI_NEW
 #define CONFIG_USB_STORAGE
 #undef CFG_OHCI_BE_CONTROLLER		/* 460EX has little endian descriptors	*/
@@ -283,6 +297,7 @@
 #define CFG_USB_OHCI_REGS_BASE	(CFG_AHB_BASE | 0xd0000)
 #define CFG_USB_OHCI_SLOT_NAME	"ppc440"
 #define CFG_USB_OHCI_MAX_ROOT_PORTS 15
+#endif
 
 /*-----------------------------------------------------------------------
  * Default environment
@@ -293,9 +308,21 @@
 
 #undef	CONFIG_BOOTARGS
 
+/* Setup some board specific values for the default environment variables */
+#ifdef CONFIG_CANYONLANDS
+#define CONFIG_HOSTNAME		canyonlands
+#define CFG_BOOTFILE		"bootfile=canyonlands/uImage\0"
+#define CFG_DTBFILE		"fdt_file=canyonlands/canyonlands.dtb\0"
+#else
+#define CONFIG_HOSTNAME		glacier
+#define CFG_BOOTFILE		"bootfile=glacier/uImage\0"
+#define CFG_DTBFILE		"fdt_file=glacier/glacier.dtb\0"
+#endif
+
 #define	CONFIG_EXTRA_ENV_SETTINGS					\
+	CFG_BOOTFILE							\
+	CFG_DTBFILE							\
 	"netdev=eth0\0"							\
-	"hostname=canyonlands\0"					\
 	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
 		"nfsroot=${serverip}:${rootpath}\0"			\
 	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
@@ -315,18 +342,16 @@
 	"flash_self=run ramargs addip addtty;"				\
 		"bootm ${kernel_addr} ${ramdisk_addr}\0"		\
 	"rootpath=/opt/eldk/ppc_4xxFP\0"				\
-	"bootfile=canyonlands/uImage\0"					\
-	"fdt_file=canyonlands/canyonlands.dtb\0"			\
 	"fdt_addr=400000\0"						\
 	"kernel_addr=fc000000\0"					\
 	"ramdisk_addr=fc200000\0"					\
 	"initrd_high=30000000\0"					\
-	"load=tftp 200000 canyonlands/u-boot.bin\0"			\
+	"load=tftp 200000 ${hostname}/u-boot.bin\0"			\
 	"update=protect off fffa0000 ffffffff;era fffa0000 ffffffff;"	\
 		"cp.b ${fileaddr} fffa0000 ${filesize};"		\
 		"setenv filesize;saveenv\0"				\
 	"upd=run load update\0"						\
-	"nload=tftp 200000 canyonlands/u-boot-nand.bin\0"		\
+	"nload=tftp 200000 ${hostname}/u-boot-nand.bin\0"		\
 	"nupdate=nand erase 0 60000;nand write 200000 0 60000;"		\
 		"setenv filesize;saveenv\0"				\
 	"nupd=run nload nupdate\0"					\
@@ -361,8 +386,6 @@
 #define CONFIG_CMD_DIAG
 #define CONFIG_CMD_EEPROM
 #define CONFIG_CMD_ELF
-#define CONFIG_CMD_EXT2
-#define CONFIG_CMD_FAT
 #define CONFIG_CMD_I2C
 #define CONFIG_CMD_IRQ
 #define CONFIG_CMD_MII
@@ -373,7 +396,11 @@
 #define CONFIG_CMD_PING
 #define CONFIG_CMD_REGINFO
 #define CONFIG_CMD_SDRAM
+#ifdef CONFIG_460EX
+#define CONFIG_CMD_EXT2
+#define CONFIG_CMD_FAT
 #define CONFIG_CMD_USB
+#endif
 
 /* Partitions */
 #define CONFIG_MAC_PARTITION
@@ -487,6 +514,8 @@
 /*
  * PPC4xx GPIO Configuration
  */
+#ifdef CONFIG_460EX
+/* 460EX: Use USB configuration */
 #define CFG_4xx_GPIO_TABLE { /*	  Out		  GPIO	Alternate1	Alternate2	Alternate3 */ \
 {											\
 /* GPIO Core 0 */									\
@@ -559,6 +588,81 @@
 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO63  Unselect via TraceSelect Bit	*/	\
 }											\
 }
+#else
+/* 460GT: Use EMAC2+3 configuration */
+#define CFG_4xx_GPIO_TABLE { /*	  Out		  GPIO	Alternate1	Alternate2	Alternate3 */ \
+{											\
+/* GPIO Core 0 */									\
+{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO0	GMC1TxD(0)	USB2HostD(0)	*/	\
+{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO1	GMC1TxD(1)	USB2HostD(1)	*/	\
+{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO2	GMC1TxD(2)	USB2HostD(2)	*/	\
+{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO3	GMC1TxD(3)	USB2HostD(3)	*/	\
+{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO4	GMC1TxD(4)	USB2HostD(4)	*/	\
+{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO5	GMC1TxD(5)	USB2HostD(5)	*/	\
+{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO6	GMC1TxD(6)	USB2HostD(6)	*/	\
+{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO7	GMC1TxD(7)	USB2HostD(7)	*/	\
+{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO8	GMC1RxD(0)	USB2OTGD(0)	*/	\
+{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO9	GMC1RxD(1)	USB2OTGD(1)	*/	\
+{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO10 GMC1RxD(2)	USB2OTGD(2)	*/	\
+{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO11 GMC1RxD(3)	USB2OTGD(3)	*/	\
+{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO12 GMC1RxD(4)	USB2OTGD(4)	*/	\
+{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO13 GMC1RxD(5)	USB2OTGD(5)	*/	\
+{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO14 GMC1RxD(6)	USB2OTGD(6)	*/	\
+{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO15 GMC1RxD(7)	USB2OTGD(7)	*/	\
+{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO16 GMC1TxER	USB2HostStop	*/	\
+{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO17 GMC1CD		USB2HostNext	*/	\
+{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO18 GMC1RxER	USB2HostDir	*/	\
+{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO19 GMC1TxEN	USB2OTGStop	*/	\
+{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO20 GMC1CRS	USB2OTGNext	*/	\
+{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO21 GMC1RxDV	USB2OTGDir	*/	\
+{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO22 NFRDY				*/	\
+{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO23 NFREN				*/	\
+{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO24 NFWEN				*/	\
+{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO25 NFCLE				*/	\
+{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO26 NFALE				*/	\
+{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO27 IRQ(0)				*/	\
+{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO28 IRQ(1)				*/	\
+{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO29 IRQ(2)				*/	\
+{GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO30 PerPar0	DMAReq2		IRQ(7)*/ \
+{GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO31 PerPar1	DMAAck2		IRQ(8)*/ \
+},											\
+{											\
+/* GPIO Core 1 */									\
+{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO32 PerPar2	EOT2/TC2	IRQ(9)*/ \
+{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO33 PerPar3	DMAReq3		IRQ(4)*/ \
+{GPIO1_BASE, GPIO_OUT, GPIO_ALT3, GPIO_OUT_1}, /* GPIO34 UART0_DCD_N	UART1_DSR_CTS_N	UART2_SOUT*/ \
+{GPIO1_BASE, GPIO_IN , GPIO_ALT3, GPIO_OUT_0}, /* GPIO35 UART0_8PIN_DSR_N UART1_RTS_DTR_N UART2_SIN*/ \
+{GPIO1_BASE, GPIO_IN , GPIO_ALT3, GPIO_OUT_0}, /* GPIO36 UART0_8PIN_CTS_N DMAAck3	UART3_SIN*/ \
+{GPIO1_BASE, GPIO_BI , GPIO_ALT2, GPIO_OUT_0}, /* GPIO37 UART0_RTS_N	EOT3/TC3	UART3_SOUT*/ \
+{GPIO1_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_1}, /* GPIO38 UART0_DTR_N	UART1_SOUT	*/	\
+{GPIO1_BASE, GPIO_IN , GPIO_ALT2, GPIO_OUT_0}, /* GPIO39 UART0_RI_N	UART1_SIN	*/	\
+{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO40 IRQ(3)				*/	\
+{GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO41 CS(1)				*/	\
+{GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO42 CS(2)				*/	\
+{GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO43 CS(3)		DMAReq1		IRQ(10)*/ \
+{GPIO1_BASE, GPIO_IN , GPIO_ALT3, GPIO_OUT_0}, /* GPIO44 CS(4)		DMAAck1		IRQ(11)*/ \
+{GPIO1_BASE, GPIO_IN , GPIO_ALT3, GPIO_OUT_0}, /* GPIO45 CS(5)		EOT/TC1		IRQ(12)*/ \
+{GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO46 PerAddr(5)	DMAReq0		IRQ(13)*/ \
+{GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO47 PerAddr(6)	DMAAck0		IRQ(14)*/ \
+{GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO48 PerAddr(7)	EOT/TC0		IRQ(15)*/ \
+{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO49  Unselect via TraceSelect Bit	*/	\
+{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO50  Unselect via TraceSelect Bit	*/	\
+{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO51  Unselect via TraceSelect Bit	*/	\
+{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO52  Unselect via TraceSelect Bit	*/	\
+{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO53  Unselect via TraceSelect Bit	*/	\
+{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO54  Unselect via TraceSelect Bit	*/	\
+{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO55  Unselect via TraceSelect Bit	*/	\
+{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO56  Unselect via TraceSelect Bit	*/	\
+{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO57  Unselect via TraceSelect Bit	*/	\
+{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO58  Unselect via TraceSelect Bit	*/	\
+{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO59  Unselect via TraceSelect Bit	*/	\
+{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO60  Unselect via TraceSelect Bit	*/	\
+{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO61  Unselect via TraceSelect Bit	*/	\
+{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO62  Unselect via TraceSelect Bit	*/	\
+{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO63  Unselect via TraceSelect Bit	*/	\
+}											\
+}
+#endif
 
 /* pass open firmware flat tree */
 #define CONFIG_OF_LIBFDT	1

include/configs/korat.h

@@ -45,10 +45,10 @@
  * Manufacturer's information serial EEPROM parameters
  */
 #define MAN_DATA_EEPROM_ADDR	0x53	/* EEPROM I2C address		*/
-#define MAN_SERIAL_NO_FIELD	2
-#define MAN_SERIAL_NO_LENGTH	13
+#define MAN_INFO_FIELD		2
+#define MAN_INFO_LENGTH		9
 #define MAN_MAC_ADDR_FIELD	3
-#define MAN_MAC_ADDR_LENGTH	17
+#define MAN_MAC_ADDR_LENGTH	12
 
 /*
  * Base addresses -- Note these are effective addresses where the actual
@@ -57,17 +57,18 @@
 #define CFG_MONITOR_LEN		(384 * 1024) /* Reserve 384 kiB for Monitor  */
 #define CFG_MALLOC_LEN		(256 * 1024) /* Reserve 256 kiB for malloc() */
 
-#define CFG_BOOT_BASE_ADDR	0xf0000000
 #define CFG_SDRAM_BASE		0x00000000	/* _must_ be 0		*/
-#define CFG_FLASH_BASE		0xfc000000	/* start of FLASH	*/
+#define CFG_FLASH0_SIZE		0x01000000
+#define CFG_FLASH0_ADDR		(-CFG_FLASH0_SIZE)
+#define CFG_FLASH1_TOP		0xF8000000
+#define CFG_FLASH1_MAX_SIZE	0x08000000
+#define CFG_FLASH1_ADDR		(CFG_FLASH1_TOP - CFG_FLASH1_MAX_SIZE)
+#define CFG_FLASH_BASE		CFG_FLASH1_ADDR	/* start of FLASH	*/
 #define CFG_MONITOR_BASE	TEXT_BASE
 #define CFG_OCM_BASE		0xe0010000	/* ocm			*/
 #define CFG_OCM_DATA_ADDR	CFG_OCM_BASE
 #define CFG_PCI_BASE		0xe0000000	/* Internal PCI regs	*/
 #define CFG_PCI_MEMBASE		0x80000000	/* mapped pci memory	*/
-#define CFG_PCI_MEMBASE1	CFG_PCI_MEMBASE  + 0x10000000
-#define CFG_PCI_MEMBASE2	CFG_PCI_MEMBASE1 + 0x10000000
-#define CFG_PCI_MEMBASE3	CFG_PCI_MEMBASE2 + 0x10000000
 
 /* Don't change either of these */
 #define CFG_PERIPHERAL_BASE	0xef600000	/* internal peripherals	*/
@@ -108,13 +109,14 @@
 /*
  * FLASH related
  */
-#define CFG_FLASH_CFI			/* The flash is CFI compatible	*/
-#define CFG_FLASH_CFI_DRIVER		/* Use common CFI driver	*/
+#define CFG_FLASH_CFI			/* The flash is CFI compatible	      */
+#define CFG_FLASH_CFI_DRIVER		/* Use common CFI driver	      */
+#define CONFIG_FLASH_CFI_LEGACY		/* Allow hard-coded config for FLASH0 */
 
-#define CFG_FLASH_BANKS_LIST	{ CFG_FLASH_BASE }
+#define CFG_FLASH_BANKS_LIST	{ CFG_FLASH1_ADDR, CFG_FLASH0_ADDR }
 
-#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks	      */
-#define CFG_MAX_FLASH_SECT	512	/* max number of sectors on one chip  */
+#define CFG_MAX_FLASH_BANKS	2	/* max number of memory banks	      */
+#define CFG_MAX_FLASH_SECT	1024	/* max number of sectors on one chip  */
 
 #define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)    */
 #define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)    */
@@ -126,12 +128,12 @@
 #define CFG_FLASH_QUIET_TEST	1	/* don't warn upon unknown flash      */
 
 #define CFG_ENV_SECT_SIZE	0x20000	/* size of one complete sector	      */
-#define CFG_ENV_ADDR		((-CFG_MONITOR_LEN)-CFG_ENV_SECT_SIZE)
+#define CFG_ENV_ADDR		(CFG_FLASH1_TOP - CFG_ENV_SECT_SIZE)
 #define	CFG_ENV_SIZE		0x2000	/* Total Size of Environment Sector   */
 
-/* Address and size of Redundant Environment Sector	*/
-#define CFG_ENV_ADDR_REDUND	(CFG_ENV_ADDR-CFG_ENV_SECT_SIZE)
-#define CFG_ENV_SIZE_REDUND	(CFG_ENV_SIZE)
+/* Address and size of Redundant Environment Sector */
+#define CFG_ENV_ADDR_REDUND	(CFG_ENV_ADDR - CFG_ENV_SECT_SIZE)
+#define CFG_ENV_SIZE_REDUND	CFG_ENV_SIZE
 
 /*
  * DDR SDRAM
@@ -144,6 +146,8 @@
 #define SPD_EEPROM_ADDRESS	{0x50}
 #define CONFIG_PROG_SDRAM_TLB
 #define CFG_DRAM_TEST
+#define CFG_MEM_TOP_HIDE	(4 << 10) /* don't use last 4kbytes	*/
+					/* 440EPx errata CHIP 11	*/
 
 /*
  * I2C
@@ -180,6 +184,7 @@
 #define CFG_BOOTFILE		"bootfile=/tftpboot/korat/uImage\0"
 #define CFG_ROOTPATH		"rootpath=/opt/eldk/ppc_4xxFP\0"
 
+/* Note: kernel_addr and ramdisk_addr assume that FLASH1 is 64 MiB. */
 #define	CONFIG_EXTRA_ENV_SETTINGS					\
 	CFG_BOOTFILE							\
 	CFG_ROOTPATH							\
@@ -197,8 +202,8 @@
 		"bootm ${kernel_addr} ${ramdisk_addr}\0"		\
 	"net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;"     \
 	        "bootm\0"						\
-	"kernel_addr=FC000000\0"					\
-	"ramdisk_addr=FC180000\0"					\
+	"kernel_addr=F4000000\0"					\
+	"ramdisk_addr=F4400000\0"					\
 	"load=tftp 200000 /tftpboot/${hostname}/u-boot.bin\0"		\
 	"update=protect off FFFA0000 FFFFFFFF;era FFFA0000 FFFFFFFF;"	\
 		"cp.b 200000 FFFA0000 60000\0"			        \
@@ -216,7 +221,7 @@
 #define CONFIG_PHY_ADDR		2	/* PHY address, See schematics	*/
 #define CONFIG_PHY_DYNAMIC_ANEG	1
 
-#define CONFIG_PHY_RESET	1	/* reset phy upon startup	*/
+#undef CONFIG_PHY_RESET			/* Don't do software PHY reset	*/
 #define CONFIG_PHY_GIGE		1	/* Include GbE speed/duplex detection */
 
 #define CONFIG_HAS_ETH0
@@ -321,6 +326,11 @@
 #define CONFIG_ZERO_BOOTDELAY_CHECK	/* check for keypress on bootdelay==0 */
 #define CONFIG_VERSION_VARIABLE 1	/* include version env variable	*/
 
+/*
+ * Korat-specific options
+ */
+#define CFG_KORAT_MAN_RESET_MS	10000	/* timeout for manufacturer reset */
+
 /*
  * PCI stuff
  */
@@ -350,12 +360,23 @@
  */
 
 /* Memory Bank 0 (NOR-FLASH) initialization				*/
+#if CFG_FLASH0_SIZE == 0x01000000
+#define CFG_EBC_PB0AP		0x04017300
+#define CFG_EBC_PB0CR		(CFG_FLASH0_ADDR | 0x0009A000)
+#elif CFG_FLASH0_SIZE == 0x04000000
 #define CFG_EBC_PB0AP		0x04017300
-#define CFG_EBC_PB0CR		(CFG_FLASH_BASE | 0x000DA000)
+#define CFG_EBC_PB0CR		(CFG_FLASH0_ADDR | 0x000DA000)
+#else
+#error Unable to configure chip select for current CFG_FLASH0_SIZE
+#endif
 
 /* Memory Bank 1 (NOR-FLASH) initialization				*/
+#if CFG_FLASH1_MAX_SIZE == 0x08000000
 #define CFG_EBC_PB1AP		0x04017300
-#define CFG_EBC_PB1CR		(0xF8000000 | 0x000DA000)
+#define CFG_EBC_PB1CR		(CFG_FLASH1_ADDR | 0x000FA000)
+#else
+#error Unable to configure chip select for current CFG_FLASH1_MAX_SIZE
+#endif
 
 /* Memory Bank 2 (CPLD) initialization					*/
 #define CFG_EBC_PB2AP		0x04017300
@@ -426,6 +447,7 @@
  * GPIO63  xxxx   x    x   (reserved for trace port)
  */
 
+#define CFG_GPIO_ATMEGA_RESET_	12
 #define CFG_GPIO_ATMEGA_SS_	13
 #define CFG_GPIO_PHY0_FIBER_SEL	27
 #define CFG_GPIO_PHY1_FIBER_SEL	28
@@ -435,6 +457,7 @@
 #define CFG_GPIO_SFP1_TX_EN_	33
 #define CFG_GPIO_PHY0_EN	45
 #define CFG_GPIO_PHY1_EN	46
+#define CFG_GPIO_RESET_PRESSED_	47
 
 /*
  * PPC440 GPIO Configuration

include/configs/lwmon5.h

@@ -1,5 +1,5 @@
 /*
- * (C) Copyright 2007
+ * (C) Copyright 2007-2008
  * Stefan Roese, DENX Software Engineering, sr@denx.de.
  *
  * This program is free software; you can redistribute it and/or
@@ -86,6 +86,8 @@
 #define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
 #define CFG_POST_ALT_WORD_ADDR	(CFG_PERIPHERAL_BASE + GPT0_COMP6)
 						/* unused GPT0 COMP reg	*/
+#define CFG_MEM_TOP_HIDE	(4 << 10) /* don't use last 4kbytes	*/
+					/* 440EPx errata CHIP 11	*/
 
 /* Additional registers for watchdog timer post test */
 
@@ -149,12 +151,8 @@
 #define CFG_MBYTES_SDRAM	(256)		/* 256MB			*/
 #define CFG_DDR_CACHED_ADDR	0x40000000	/* setup 2nd TLB cached here	*/
 #define CONFIG_DDR_DATA_EYE	1		/* use DDR2 optimization	*/
-#if 0 /* test-only: disable ECC for now */
 #define CONFIG_DDR_ECC		1		/* enable ECC			*/
 #define CFG_POST_ECC_ON		CFG_POST_ECC
-#else
-#define CFG_POST_ECC_ON		0
-#endif
 
 /* POST support */
 #define CONFIG_POST		(CFG_POST_CACHE    | \

include/configs/sequoia.h

@@ -221,6 +221,8 @@
 #if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
 #define CONFIG_DDR_DATA_EYE		/* use DDR2 optimization	*/
 #endif
+#define CFG_MEM_TOP_HIDE	(4 << 10) /* don't use last 4kbytes	*/
+					/* 440EPx errata CHIP 11	*/
 
 /*
  * I2C
@@ -275,7 +277,7 @@
 		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
 		":${hostname}:${netdev}:off panic=1\0"			\
 	"addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
-	"addmisc=setenv bootargs ${bootargs} mem=${mem}\0"		\
+	"addmisc=setenv bootargs ${bootargs}\0"				\
 	"flash_nfs=run nfsargs addip addtty addmisc;"			\
 		"bootm ${kernel_addr}\0"				\
 	"flash_self=run ramargs addip addtty addmisc;"			\

include/ppc440.h

@@ -2023,9 +2023,13 @@
 #define malrxctp2r  (MAL_DCR_BASE+0x42) /* RX 2 Channel table pointer reg   */
 #define malrxctp3r  (MAL_DCR_BASE+0x43) /* RX 3 Channel table pointer reg   */
 #define malrxctp8r  (MAL_DCR_BASE+0x48) /* RX 8 Channel table pointer reg   */
+#define malrxctp16r (MAL_DCR_BASE+0x50) /* RX 16 Channel table pointer reg  */
+#define malrxctp24r (MAL_DCR_BASE+0x58) /* RX 24 Channel table pointer reg  */
 #define malrcbs2    (MAL_DCR_BASE+0x62) /* RX 2 Channel buffer size reg	    */
 #define malrcbs3    (MAL_DCR_BASE+0x63) /* RX 3 Channel buffer size reg	    */
 #define malrcbs8    (MAL_DCR_BASE+0x68) /* RX 8 Channel buffer size reg	    */
+#define malrcbs16   (MAL_DCR_BASE+0x70) /* RX 16 Channel buffer size reg    */
+#define malrcbs24   (MAL_DCR_BASE+0x78) /* RX 24 Channel buffer size reg    */
 #endif /* CONFIG_440GX */
 
 

include/ppc4xx_enet.h

@@ -213,6 +213,10 @@ typedef struct emac_4xx_hw_st {
 #define RGMII_FER		(RGMII_BASE + 0x00)
 #define RGMII_SSR		(RGMII_BASE + 0x04)
 
+#if defined(CONFIG_460GT)
+#define RGMII1_BASE_OFFSET	0x100
+#endif
+
 /* RGMII Function Enable (FER) Register Bit Definitions */
 /* Note: for EMAC 2 and 3 only, 440GX only */
 #define RGMII_FER_DIS		(0x00)

lib_ppc/board.c

@@ -120,6 +120,10 @@ DECLARE_GLOBAL_DATA_PTR;
 #define	TOTAL_MALLOC_LEN	CFG_MALLOC_LEN
 #endif
 
+#if !defined(CFG_MEM_TOP_HIDE)
+#define CFG_MEM_TOP_HIDE	0
+#endif
+
 extern ulong __init_end;
 extern ulong _end;
 ulong monitor_flash_len;
@@ -428,6 +432,7 @@ void board_init_f (ulong bootflag)
 	 * relocate the code and continue running from DRAM.
 	 *
 	 * Reserve memory at end of RAM for (top down in that order):
+	 *  - area that won't get touched by U-Boot and Linux (optional)
 	 *  - kernel log buffer
 	 *  - protected RAM
 	 *  - LCD framebuffer
@@ -436,6 +441,18 @@ void board_init_f (ulong bootflag)
 	 */
 	len = (ulong)&_end - CFG_MONITOR_BASE;
 
+	/*
+	 * Subtract specified amount of memory to hide so that it won't
+	 * get "touched" at all by U-Boot. By fixing up gd->ram_size
+	 * the Linux kernel should now get passed the now "corrected"
+	 * memory size and won't touch it either. This should work
+	 * for arch/ppc and arch/powerpc. Only Linux board ports in
+	 * arch/powerpc with bootwrapper support, that recalculate the
+	 * memory size from the SDRAM controller setup will have to
+	 * get fixed.
+	 */
+	gd->ram_size -= CFG_MEM_TOP_HIDE;
+
 #ifndef CONFIG_MAX_MEM_MAPPED
 #define CONFIG_MAX_MEM_MAPPED (256 << 20)
 #endif