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@@ -96,7 +96,7 @@ _armboot_real_end:
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*/
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*/
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.globl _uboot_reloc
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.globl _uboot_reloc
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_uboot_reloc:
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_uboot_reloc:
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- .word CFG_DRAM_BASE + CFG_DRAM_SIZE - CFG_MONITOR_LEN
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+ .word TEXT_BASE
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#ifdef CONFIG_USE_IRQ
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#ifdef CONFIG_USE_IRQ
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/* IRQ stack memory (calculated at run-time) */
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/* IRQ stack memory (calculated at run-time) */
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@@ -130,7 +130,6 @@ relocate: /* relocate U-Boot to RAM */
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ldr r2, _armboot_start
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ldr r2, _armboot_start
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ldr r3, _armboot_end
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ldr r3, _armboot_end
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sub r2, r3, r2 /* r2 <- size of armboot */
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sub r2, r3, r2 /* r2 <- size of armboot */
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-/* ldr r1, _uboot_reloc / * r1 <- destination address */
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ldr r1, _TEXT_BASE
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ldr r1, _TEXT_BASE
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add r2, r0, r2 /* r2 <- source end address */
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add r2, r0, r2 /* r2 <- source end address */
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@@ -176,7 +175,7 @@ cpuspeed: .word CFG_CPUSPEED
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/* RS: ??? */
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/* RS: ??? */
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.macro CPWAIT
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.macro CPWAIT
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- mrc p15,0,r0,c2,c0,0
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+ mrc p15,0,r0,c2,c0,0
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mov r0,r0
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mov r0,r0
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sub pc,pc,#4
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sub pc,pc,#4
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.endm
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.endm
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@@ -207,23 +206,23 @@ cpu_init_crit:
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ldr r0, =0x2001 /* enable access to all coproc. */
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ldr r0, =0x2001 /* enable access to all coproc. */
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mcr p15, 0, r0, c15, c1, 0
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mcr p15, 0, r0, c15, c1, 0
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- CPWAIT
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+ CPWAIT
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mcr p15, 0, r0, c7, c10, 4 /* drain the write & fill buffers */
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mcr p15, 0, r0, c7, c10, 4 /* drain the write & fill buffers */
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- CPWAIT
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+ CPWAIT
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mcr p15, 0, r0, c7, c7, 0 /* flush Icache, Dcache and BTB */
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mcr p15, 0, r0, c7, c7, 0 /* flush Icache, Dcache and BTB */
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- CPWAIT
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+ CPWAIT
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mcr p15, 0, r0, c8, c7, 0 /* flush instuction and data TLBs */
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mcr p15, 0, r0, c8, c7, 0 /* flush instuction and data TLBs */
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- CPWAIT
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+ CPWAIT
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/* Enable the Icache */
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/* Enable the Icache */
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/*
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/*
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mrc p15, 0, r0, c1, c0, 0
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mrc p15, 0, r0, c1, c0, 0
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orr r0, r0, #0x1800
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orr r0, r0, #0x1800
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mcr p15, 0, r0, c1, c0, 0
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mcr p15, 0, r0, c1, c0, 0
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- CPWAIT
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+ CPWAIT
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*/
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*/
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mov pc, lr
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mov pc, lr
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