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@@ -41,6 +41,15 @@ DECLARE_GLOBAL_DATA_PTR;
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#if CONFIG_POST & CFG_POST_BSPEC3
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+/* Testpattern for fpga memorytest */
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+static uint pattern[] = {
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+ 0x55555555,
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+ 0xAAAAAAAA,
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+ 0xAA5555AA,
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+ 0x55AAAA55,
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+ 0x0
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+};
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+
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static int one_scratch_test(uint value)
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{
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uint read_value;
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@@ -60,9 +69,42 @@ static int one_scratch_test(uint value)
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return ret;
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}
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+/* FPGA Memory-pattern-test */
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+static int fpga_mem_test(void * address)
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+{
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+ int ret = 1;
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+ uint read_value;
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+ uint old_value;
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+ uint i = 0;
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+ /* save content */
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+ old_value = in_be32(address);
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+
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+ while (pattern[i] != 0) {
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+ out_be32(address, pattern[i]);
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+ /* read other location (protect against data lines capacity) */
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+ ret = in_be16((void *)FPGA_VERSION_REG);
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+ /* verify test pattern */
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+ read_value = in_be32(address);
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+
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+ if (read_value != pattern[i]) {
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+ post_log("FPGA Memory test failed.");
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+ post_log(" write %08X, read %08X at address %08X\n",
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+ pattern[i], read_value, address);
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+ ret = 1;
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+ goto out;
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+ }
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+ i++;
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+ }
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+
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+ ret = 0;
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+out:
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+ out_be32(address, old_value);
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+ return ret;
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+}
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/* Verify FPGA, get version & memory size */
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int fpga_post_test(int flags)
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{
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+ uint address;
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uint old_value;
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ushort version;
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uint read_value;
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@@ -88,6 +130,14 @@ int fpga_post_test(int flags)
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read_value = get_ram_size((void *)CFG_FPGA_BASE_1, 0x4000);
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post_log("FPGA RAM size: %d bytes\n", read_value);
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+ for (address = 0; address < 0x1000; address++) {
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+ if (fpga_mem_test((void *)(FPGA_RAM_START + 4*address)) == 1) {
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+ ret = 1;
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+ goto out;
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+ }
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+ }
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+
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+out:
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return ret;
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}
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