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+Freescale MPC7448hpc2 (Taiga) board
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+===================================
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+
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+Created 08/11/2006 Roy Zang
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+--------------------------
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+MPC7448hpc2 (Taiga) board is a high-performance PowerPC server reference
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+design, which is optimized for high speed throughput between the processor and
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+the memory, disk drive and Ethernet port subsystems.
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+
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+MPC7448hpc2(Taiga) is designed to the micro-ATX chassis, allowing it to be
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+used in 1U or 2U rack-mount chassis¡¯, as well as in standard ATX/Micro-ATX
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+chassis.
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+
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+Building U-Boot
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+------------------
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+The mpc7448hpc2 code base is known to compile using:
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+ Binutils 2.15, Gcc 3.4.3, Glibc 2.3.3
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+
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+ $ make mpc7448hpc2_config
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+ Configuring for mpc7448hpc2 board...
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+
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+ $ make
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+
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+Memory Map
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+----------
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+
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+The memory map is setup for Linux to operate properly.
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+
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+The mapping is:
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+
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+ Range Start Range End Definition Size
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+
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+ 0x0000_0000 0x7fff_ffff DDR 2G
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+ 0xe000_0000 0xe7ff_ffff PCI Memory 128M
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+ 0xfa00_0000 0xfaff_ffff PCI IO 16M
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+ 0xfb00_0000 0xfbff_ffff PCI Config 16M
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+ 0xfc00_0000 0xfc0f_ffff NVRAM/CADMUS 1M
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+ 0xfe00_0000 0xfeff_ffff PromJet 16M
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+ 0xff00_0000 0xff80_0000 FLASH (boot flash) 8M
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+ 0xff80_0000 0xffff_ffff FLASH (second half flash) 8M
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+
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+
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+Using Flash
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+-----------
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+
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+The MPC7448hpc2 board has two "banks" of flash, each 8MB in size
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+(2^23 = 0x00800000).
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+
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+Note: the "bank" here refers to half of the flash. In fact, there is only one
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+bank of flash, which is divided into low and high half. Each is controlled by
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+the most significant bit of the address bus. The so called "bank" is only for
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+convenience.
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+
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+There is a switch which allows the "bank" to be selected. The switch
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+settings for updating flash are given below.
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+
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+The u-boot commands for copying the boot-bank into the secondary bank are
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+as follows:
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+
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+ erase ff800000 ff880000
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+ cp.b ff000000 ff800000 80000
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+
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+U-boot commands for downloading an image via tftp and flashing
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+it into the secondary bank:
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+
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+ tftp 10000 <u-boot.bin.image>
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+ erase ff000000 ff080000
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+ cp.b 10000 ff000000 80000
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+
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+
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+After copying the image into the second bank of flash, be sure to toggle
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+SW3[4] on board before resetting the board in order to set the
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+secondary bank as the boot-bank.
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+
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+
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+Board Switches
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+----------------------
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+
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+
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+Most switches on the board should not be changed. The most frequent
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+user-settable switches on the board are used to configure
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+the flash banks and determining the PCI frequency.
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+
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+SW1[1-5]: Processor core voltage
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+
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+ 12345 Core Voltage
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+ -----
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+ SW1=01111 1.000V.
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+ SW1=01101 1.100V.
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+ SW1=01011 1.200V.
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+ SW1=01001 1.300V only for MPC7447A.
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+
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+
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+SW2[1-6]: CPU core frequency
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+
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+ CPU Core Frequency (MHz)
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+ Bus Frequency
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+ 123456 100 133 167 200 Ratio
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+
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+ ------
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+ SW2=101100 500 667 833 1000 5x
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+ SW2=100100 550 733 917 1100 5.5x
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+ SW2=110100 600 800 1000 1200 6x
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+ SW2=010100 650 866 1083 1300 6.5x
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+ SW2=001000 700 930 1167 1400 7x
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+ SW2=000100 750 1000 1250 1500 7.5x
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+ SW2=110000 800 1066 1333 1600 8x
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+ SW2=011000 850 1333 1417 1700 8.5x only for MPC7447A
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+ SW2=011110 900 1200 1500 1800 9x
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+
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+This table shows only a subset of available frequency options; see the CPU
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+hardware specifications for more information.
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+
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+
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+SW2[7-8]: Bus Protocol and CPU Reset Option
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+
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+ 7
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+ -
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+ SW2=0 System bus uses MPX bus protocol
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+ SW2=1 System bus uses 60x bus protocol
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+
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+ 8
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+ -
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+ SW2=0 TSI108 can cause CPU reset
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+ SW2=1 TSI108 can not cause CPU reset
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+
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+
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+SW3[1-8] system options
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+
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+ 123
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+ ---
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+ SW3=xxx Connected to GPIO[0:2] on TSI108
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+
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+ 4
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+ -
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+ SW3=0 CPU boots from low half of flash
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+ SW3=1 CPU boots from high half of flash
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+
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+ 5
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+ -
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+ SW3=0 SATA and slot2 connected to PCI bus
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+ SW3=1 Only slot1 connected to PCI bus
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+
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+ 6
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+ -
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+ SW3=0 USB connected to PCI bus
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+ SW3=1 USB disconnected from PCI bus
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+
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+ 7
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+ -
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+ SW3=0 Flash is write protected
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+ SW3=1 Flash is NOT write protected
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+
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+ 8
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+ -
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+ SW3=0 CPU will boot from flash
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+ SW3=1 CPU will boot from PromJet
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+
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+SW4[1-3]: System bus frequency
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+
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+ Bus Frequency (MHz)
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+ ---
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+ SW4=010 183
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+ SW4=011 100
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+ SW4=100 133
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+ SW4=101 166 only for MPC7447A
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+ SW4=110 200 only for MPC7448
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+ others reserved
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+
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+
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+SW4[4-6]: DDR2 SDRAM frequency
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+
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+ Bus Frequency (MHz)
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+ ---
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+ SW4=000 external clock
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+ SW4=011 system clock
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+ SW4=100 133
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+ SW4=101 166
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+ SW4=110 200
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+ others reserved
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+
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+
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+SW4[7-8]: PCI/PCI-X frequency control
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+ 7
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+ -
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+ SW4=0 PCI/PCI-X bus operates normally
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+ SW4=1 PCI bus forced to PCI-33 mode
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+
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+ 8
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+ -
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+ SW4=0 PCI-X mode at 133 MHz allowed
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+ SW4=1 PCI-X mode limited to 100 MHz
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+
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roy zang