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@@ -55,7 +55,7 @@ int usb_cpu_init(void)
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while (readl(UHCHR) & UHCHR_FSBIR)
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udelay(1);
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-#if defined(CONFIG_CPU_MONAHANS)
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+#if defined(CONFIG_CPU_MONAHANS) || defined(CONFIG_PXA27X)
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writel(readl(UHCHR) & ~UHCHR_SSEP0, UHCHR);
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#endif
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#if defined(CONFIG_CPU_PXA27X)
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@@ -75,7 +75,7 @@ int usb_cpu_stop(void)
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writel(readl(UHCCOMS) | UHCCOMS_HCR, UHCCOMS);
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udelay(10);
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-#if defined(CONFIG_CPU_MONAHANS)
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+#if defined(CONFIG_CPU_MONAHANS) || defined(CONFIG_PXA27X)
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writel(readl(UHCHR) | UHCHR_SSEP0, UHCHR);
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#endif
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#if defined(CONFIG_CPU_PXA27X)
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