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@@ -115,21 +115,8 @@ int clk_get(enum davinci_clk_ids id)
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out:
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out:
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return pll_out;
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return pll_out;
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}
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}
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-#ifdef CONFIG_DISPLAY_CPUINFO
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-int print_cpuinfo(void)
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-{
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- printf("Cores: ARM %d MHz",
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- clk_get(DAVINCI_ARM_CLKID) / 1000000);
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- printf("\nDDR: %d MHz\n",
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- /* DDR PHY uses an x2 input clock */
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- clk_get(0x10001) / 1000000);
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- return 0;
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-}
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-#endif
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#else /* CONFIG_SOC_DA8XX */
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#else /* CONFIG_SOC_DA8XX */
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-#ifdef CONFIG_DISPLAY_CPUINFO
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-
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static unsigned pll_div(volatile void *pllbase, unsigned offset)
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static unsigned pll_div(volatile void *pllbase, unsigned offset)
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{
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{
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u32 div;
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u32 div;
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@@ -185,36 +172,6 @@ static unsigned pll_sysclk_mhz(unsigned pll_addr, unsigned div)
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return DIV_ROUND_UP(base, 1000 * pll_div(pllbase, div));
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return DIV_ROUND_UP(base, 1000 * pll_div(pllbase, div));
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}
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}
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-int print_cpuinfo(void)
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-{
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- /* REVISIT fetch and display CPU ID and revision information
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- * too ... that will matter as more revisions appear.
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- */
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-#if defined(CONFIG_SOC_DM365)
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- printf("Cores: ARM %d MHz",
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- pll_sysclk_mhz(DAVINCI_PLL_CNTRL1_BASE, ARM_PLLDIV));
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-#else
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- printf("Cores: ARM %d MHz",
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- pll_sysclk_mhz(DAVINCI_PLL_CNTRL0_BASE, ARM_PLLDIV));
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-#endif
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-
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-#ifdef DSP_PLLDIV
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- printf(", DSP %d MHz",
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- pll_sysclk_mhz(DAVINCI_PLL_CNTRL0_BASE, DSP_PLLDIV));
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-#endif
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-
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- printf("\nDDR: %d MHz\n",
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- /* DDR PHY uses an x2 input clock */
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-#if defined(CONFIG_SOC_DM365)
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- pll_sysclk_mhz(DAVINCI_PLL_CNTRL0_BASE, DDR_PLLDIV)
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- / 2);
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-#else
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- pll_sysclk_mhz(DAVINCI_PLL_CNTRL1_BASE, DDR_PLLDIV)
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- / 2);
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-#endif
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- return 0;
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-}
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-
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#ifdef DAVINCI_DM6467EVM
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#ifdef DAVINCI_DM6467EVM
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unsigned int davinci_arm_clk_get()
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unsigned int davinci_arm_clk_get()
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{
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{
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@@ -228,7 +185,6 @@ unsigned int davinci_clk_get(unsigned int div)
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return pll_sysclk_mhz(DAVINCI_PLL_CNTRL0_BASE, div) * 1000000;
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return pll_sysclk_mhz(DAVINCI_PLL_CNTRL0_BASE, div) * 1000000;
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}
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}
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#endif
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#endif
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-#endif /* CONFIG_DISPLAY_CPUINFO */
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#endif /* !CONFIG_SOC_DA8XX */
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#endif /* !CONFIG_SOC_DA8XX */
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/*
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/*
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