MPC8308RDB: various clean ups

This patch cleans up the Freescale MPC8308RDB Development board support.
Things fixed:
 - Removed unused PCIE2 definitions from configuration
 - SICR{L,H} defines used for System I/O Configuration Registers values
   instead of hardcoding
 - CONFIG_SYS_SCCR_PCIEXP1CM used to enable PCIE clock instead of
   writing to SCCR from the board code
 - sleep mode stuff removed as MPC8308 has no support for deep sleep and
   PMCCR1 register. board_early_init_f() removed.
 - MPC8308 has no ERRATA for DDR controller so workaround removed
 - 'assignment in if statement' issues solved
 - use LBLAWAR_* defines instead of hardcoding

Signed-off-by: Ilya Yanok <yanok@emcraft.com>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>

board/freescale/mpc8308rdb/mpc8308rdb.c

@@ -36,16 +36,6 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
-int board_early_init_f(void)
-{
-	immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
-
-	if (in_be32(&im->pmc.pmccr1) & PMCCR1_POWER_OFF)
-		gd->flags |= GD_FLG_SILENT;
-
-	return 0;
-}
-
 static u8 read_board_info(void)
 {
 	u8 val8;
@@ -96,16 +86,12 @@ void pci_init_board(void)
 {
 	immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
 	sysconf83xx_t *sysconf = &immr->sysconf;
-	clk83xx_t *clk = (clk83xx_t *)&immr->clk;
 	law83xx_t *pcie_law = sysconf->pcielaw;
 	struct pci_region *pcie_reg[] = { pcie_regions_0 };
 
 	fsl_setup_serdes(CONFIG_FSL_SERDES1, FSL_SERDES_PROTO_PEX,
 					FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V);
 
-	clrsetbits_be32(&clk->sccr, SCCR_PCIEXP1CM ,
-				    SCCR_PCIEXP1CM_1);
-
 	/* Deassert the resets in the control register */
 	out_be32(&sysconf->pecr1, 0xE0008000);
 	udelay(2000);
@@ -146,12 +132,14 @@ int board_eth_init(bd_t *bis)
 	int rv, num_if = 0;
 
 	/* Initialize TSECs first */
-	if ((rv = cpu_eth_init(bis)) >= 0)
+	rv = cpu_eth_init(bis);
+	if (rv >= 0)
 		num_if += rv;
 	else
 		printf("ERROR: failed to initialize TSECs.\n");
 
-	if ((rv = pci_eth_init(bis)) >= 0)
+	rv = pci_eth_init(bis);
+	if (rv >= 0)
 		num_if += rv;
 	else
 		printf("ERROR: failed to initialize PCI Ethernet.\n");

board/freescale/mpc8308rdb/sdram.c

@@ -38,20 +38,6 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
-static void resume_from_sleep(void)
-{
-	u32 magic = *(u32 *)0;
-
-	typedef void (*func_t)(void);
-	func_t resume = *(func_t *)4;
-
-	if (magic == 0xf5153ae5)
-		resume();
-
-	gd->flags &= ~GD_FLG_SILENT;
-	puts("\nResume from sleep failed: bad magic word\n");
-}
-
 /* Fixed sdram init -- doesn't use serial presence detect.
  *
  * This is useful for faster booting in configs where the RAM is unlikely
@@ -68,12 +54,6 @@ static long fixed_sdram(void)
 	out_be32(&im->sysconf.ddrlaw[0].ar, LBLAWAR_EN | (msize_log2 - 1));
 	out_be32(&im->sysconf.ddrcdr, CONFIG_SYS_DDRCDR_VALUE);
 
-	/*
-	 * Erratum DDR3 requires a 50ms delay after clearing DDRCDR[DDR_cfg],
-	 * or the DDR2 controller may fail to initialize correctly.
-	 */
-	udelay(50000);
-
 	out_be32(&im->ddr.csbnds[0].csbnds, (msize - 1) >> 24);
 	out_be32(&im->ddr.cs_config[0], CONFIG_SYS_DDR_CS0_CONFIG);
 
@@ -86,13 +66,7 @@ static long fixed_sdram(void)
 	out_be32(&im->ddr.timing_cfg_2, CONFIG_SYS_DDR_TIMING_2);
 	out_be32(&im->ddr.timing_cfg_0, CONFIG_SYS_DDR_TIMING_0);
 
-	if (in_be32(&im->pmc.pmccr1) & PMCCR1_POWER_OFF) {
-		out_be32(&im->ddr.sdram_cfg,
-			CONFIG_SYS_DDR_SDRAM_CFG | SDRAM_CFG_BI);
-	} else {
-		out_be32(&im->ddr.sdram_cfg, CONFIG_SYS_DDR_SDRAM_CFG);
-	}
-
+	out_be32(&im->ddr.sdram_cfg, CONFIG_SYS_DDR_SDRAM_CFG);
 	out_be32(&im->ddr.sdram_cfg2, CONFIG_SYS_DDR_SDRAM_CFG2);
 	out_be32(&im->ddr.sdram_mode, CONFIG_SYS_DDR_MODE);
 	out_be32(&im->ddr.sdram_mode2, CONFIG_SYS_DDR_MODE2);
@@ -118,9 +92,6 @@ phys_size_t initdram(int board_type)
 	/* DDR SDRAM */
 	msize = fixed_sdram();
 
-	if (in_be32(&im->pmc.pmccr1) & PMCCR1_POWER_OFF)
-		resume_from_sleep();
-
 	/* return total bus SDRAM size(bytes)  -- DDR */
 	return msize;
 }

include/configs/MPC8308RDB.h

@@ -85,10 +85,27 @@
 /*
  * System IO Config
  */
-#define CONFIG_SYS_SICRH	0x01b7d103
-#define CONFIG_SYS_SICRL	0x00000040 /* 3.3V, no delay */
-
-#define CONFIG_BOARD_EARLY_INIT_F /* call board_pre_init */
+#define CONFIG_SYS_SICRH (\
+	SICRH_ESDHC_A_SD |\
+	SICRH_ESDHC_B_SD |\
+	SICRH_ESDHC_C_SD |\
+	SICRH_GPIO_A_TSEC2 |\
+	SICRH_GPIO_B_TSEC2_GTX_CLK125 |\
+	SICRH_IEEE1588_A_GPIO |\
+	SICRH_USB |\
+	SICRH_GTM_GPIO |\
+	SICRH_IEEE1588_B_GPIO |\
+	SICRH_ETSEC2_CRS |\
+	SICRH_GPIOSEL_1 |\
+	SICRH_TMROBI_V3P3 |\
+	SICRH_TSOBI1_V2P5 |\
+	SICRH_TSOBI2_V2P5)	/* 0x01b7d103 */
+#define CONFIG_SYS_SICRL (\
+	SICRL_SPI_PF0 |\
+	SICRL_UART_PF0 |\
+	SICRL_IRQ_PF0 |\
+	SICRL_I2C2_PF0 |\
+	SICRL_ETSEC1_GTX_CLK125)	/* 0x00000040 */
 
 /*
  * IMMR new address
@@ -218,7 +235,7 @@
 
 /* Window base at flash base */
 #define CONFIG_SYS_LBLAWBAR0_PRELIM	CONFIG_SYS_FLASH_BASE
-#define CONFIG_SYS_LBLAWAR0_PRELIM	0x80000016 /* 8MB window size */
+#define CONFIG_SYS_LBLAWAR0_PRELIM	(LBLAWAR_EN | LBLAWAR_8MB)
 
 #define CONFIG_SYS_BR0_PRELIM	(\
 		CONFIG_SYS_FLASH_BASE	/* Flash Base address */	|\
@@ -260,7 +277,7 @@
 				/* 0xFFFF8396 */
 
 #define CONFIG_SYS_LBLAWBAR1_PRELIM	CONFIG_SYS_NAND_BASE
-#define CONFIG_SYS_LBLAWAR1_PRELIM	0x8000000E	/* 32KB  */
+#define CONFIG_SYS_LBLAWAR1_PRELIM	(LBLAWAR_EN | LBLAWAR_32KB)
 
 #ifdef CONFIG_VSC7385_ENET
 #define CONFIG_TSEC2
@@ -270,7 +287,7 @@
 /* Access window base at VSC7385 base */
 #define CONFIG_SYS_LBLAWBAR2_PRELIM	CONFIG_SYS_VSC7385_BASE
 /* Access window size 128K */
-#define CONFIG_SYS_LBLAWAR2_PRELIM	0x80000010
+#define CONFIG_SYS_LBLAWAR2_PRELIM	(LBLAWAR_EN | LBLAWAR_128KB)
 /* The flash address and size of the VSC7385 firmware image */
 #define CONFIG_VSC7385_IMAGE		0xFE7FE000
 #define CONFIG_VSC7385_IMAGE_SIZE	8192
@@ -335,19 +352,8 @@
 #define CONFIG_SYS_PCIE1_IO_PHYS	0xB1000000
 #define CONFIG_SYS_PCIE1_IO_SIZE	0x00800000
 
-/*
- * Fake PCIE2 definitions: there is no PCIE2 on this board but the code
- * in arch/powerpc/cpu/mpc83xx/pcie.c doesn't compile without this
- */
-#define CONFIG_SYS_PCIE2_BASE		0xC0000000
-#define CONFIG_SYS_PCIE2_MEM_BASE	0xC0000000
-#define CONFIG_SYS_PCIE2_MEM_PHYS	0xC0000000
-#define CONFIG_SYS_PCIE2_MEM_SIZE	0x10000000
-#define CONFIG_SYS_PCIE2_CFG_BASE	0xD0000000
-#define CONFIG_SYS_PCIE2_CFG_SIZE	0x01000000
-#define CONFIG_SYS_PCIE2_IO_BASE	0x00000000
-#define CONFIG_SYS_PCIE2_IO_PHYS	0xD1000000
-#define CONFIG_SYS_PCIE2_IO_SIZE	0x00800000
+/* enable PCIE clock */
+#define CONFIG_SYS_SCCR_PCIEXP1CM	1
 
 #define CONFIG_PCI
 #define CONFIG_PCIE