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@@ -282,8 +282,13 @@ static const u16 sh_eth_offset_fast_sh4[SH_ETH_MAX_REGISTER_OFFSET] = {
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#define SH_ETH_TYPE_GETHER
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#define BASE_IO_ADDR 0xfee00000
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#elif defined(CONFIG_CPU_SH7757)
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+#if defined(CONFIG_SH_ETHER_USE_GETHER)
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+#define SH_ETH_TYPE_GETHER
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+#define BASE_IO_ADDR 0xfee00000
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+#else
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#define SH_ETH_TYPE_ETHER
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#define BASE_IO_ADDR 0xfef00000
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+#endif
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#elif defined(CONFIG_CPU_SH7724)
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#define SH_ETH_TYPE_ETHER
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#define BASE_IO_ADDR 0xA4600000
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@@ -331,7 +336,11 @@ enum DMAC_T_BIT {
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/* GECMR */
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enum GECMR_BIT {
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+#if defined(CONFIG_CPU_SH7757)
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+ GECMR_1000B = 0x20, GECMR_100B = 0x01, GECMR_10B = 0x00,
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+#else
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GECMR_1000B = 0x01, GECMR_100B = 0x04, GECMR_10B = 0x00,
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+#endif
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};
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/* EDRRR*/
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