vf610twr: DDR tuning to fix boot issues in cold environments

Hangs during the boot were observed on some boards at POR at
temperatures below 0 celsius degrees.

Problem was mainly due to the Read Level and Read Gate Level
parameter in Register CR110.It would seem that a Read on Byte
lane 1 is so fast, there can be no time for delay before start
reading that signal.

Signed-off-by: Mark Middleton <b18548@freescale.com>
Signed-off-by: Jiri Kotzian <b36968@freescale.com>
Signed-off-by: Juan Gutierrez <b44802@freescale.com>
Signed-off-by: Anthony Felice <tony.felice@timesys.com>

arch/arm/include/asm/arch-vf610/imx-regs.h

@@ -119,7 +119,7 @@
 #define DDRMC_PHY_DQS_TIMING				0x00002615
 #define DDRMC_PHY_CTRL					0x00210000
 #define DDRMC_PHY_MASTER_CTRL				0x0001012a
-#define DDRMC_PHY_SLAVE_CTRL				0x00002000
+#define DDRMC_PHY_SLAVE_CTRL				0x00002400
 #define DDRMC_PHY_OFF					0x00000000
 #define DDRMC_PHY_PROC_PAD_ODT				0x00010101
 
@@ -212,8 +212,8 @@
 #define DDRMC_CR97_WRLVL_EN				(1 << 24)
 #define DDRMC_CR98_WRLVL_DL_0				(0)
 #define DDRMC_CR99_WRLVL_DL_1				(0)
-#define DDRMC_CR102_RDLVL_GT_REGEN			(1 << 16)
-#define DDRMC_CR102_RDLVL_REG_EN			(1 << 8)
+#define DDRMC_CR102_RDLVL_GT_REGEN(v)			(((v) & 0x1) << 16)
+#define DDRMC_CR102_RDLVL_REG_EN(v)			(((v) & 0x1) << 8)
 #define DDRMC_CR105_RDLVL_DL_0(v)			(((v) & 0xff) << 8)
 #define DDRMC_CR106_RDLVL_GTDL_0(v)			((v) & 0xff)
 #define DDRMC_CR110_RDLVL_DL_1(v)			((v) & 0xff)

board/freescale/vf610twr/vf610twr.c

@@ -109,7 +109,6 @@ void ddr_phy_init(void)
 
 	writel(DDRMC_PHY_DQ_TIMING, &ddrmr->phy[0]);
 	writel(DDRMC_PHY_DQ_TIMING, &ddrmr->phy[16]);
-	writel(DDRMC_PHY_DQ_TIMING, &ddrmr->phy[32]);
 
 	writel(DDRMC_PHY_DQS_TIMING, &ddrmr->phy[1]);
 	writel(DDRMC_PHY_DQS_TIMING, &ddrmr->phy[17]);
@@ -214,12 +213,13 @@ void ddr_ctrl_init(void)
 	writel(DDRMC_CR98_WRLVL_DL_0, &ddrmr->cr[98]);
 	writel(DDRMC_CR99_WRLVL_DL_1, &ddrmr->cr[99]);
 
-	writel(DDRMC_CR102_RDLVL_GT_REGEN | DDRMC_CR102_RDLVL_REG_EN,
+	writel(DDRMC_CR102_RDLVL_GT_REGEN(0) | DDRMC_CR102_RDLVL_REG_EN(0),
 		&ddrmr->cr[102]);
 
-	writel(DDRMC_CR105_RDLVL_DL_0(0), &ddrmr->cr[105]);
-	writel(DDRMC_CR106_RDLVL_GTDL_0(4), &ddrmr->cr[106]);
-	writel(DDRMC_CR110_RDLVL_GTDL_1(4), &ddrmr->cr[110]);
+	writel(DDRMC_CR105_RDLVL_DL_0(12), &ddrmr->cr[105]);
+	writel(DDRMC_CR106_RDLVL_GTDL_0(0), &ddrmr->cr[106]);
+	writel(DDRMC_CR110_RDLVL_GTDL_1(0) | DDRMC_CR110_RDLVL_DL_1(12),
+		 &ddrmr->cr[110]);
 	writel(DDRMC_CR114_RDLVL_GTDL_2(0), &ddrmr->cr[114]);
 	writel(DDRMC_CR115_RDLVL_GTDL_2(0), &ddrmr->cr[115]);