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@@ -199,7 +199,7 @@ static void set_timing_cfg_0(fsl_ddr_cfg_regs_t *ddr)
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unsigned char act_pd_exit_mclk;
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/* Precharge powerdown exit timing (tXP). */
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unsigned char pre_pd_exit_mclk;
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- /* Precharge powerdown exit timing (tAXPD). */
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+ /* ODT powerdown exit timing (tAXPD). */
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unsigned char taxpd_mclk;
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/* Mode register set cycle time (tMRD). */
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unsigned char tmrd_mclk;
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@@ -211,13 +211,13 @@ static void set_timing_cfg_0(fsl_ddr_cfg_regs_t *ddr)
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* we use the tXP instead of it.
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* tXP=max(3nCK, 7.5ns) for DDR3.
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* spec has not the tAXPD, we use
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- * tAXPD=8, need design to confirm.
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+ * tAXPD=1, need design to confirm.
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*/
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int tXP = max((get_memory_clk_period_ps() * 3), 7500); /* unit=ps */
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act_pd_exit_mclk = picos_to_mclk(tXP);
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/* Mode register MR0[A12] is '1' - fast exit */
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pre_pd_exit_mclk = act_pd_exit_mclk;
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- taxpd_mclk = 8;
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+ taxpd_mclk = 1;
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tmrd_mclk = 4;
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/* set the turnaround time */
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trwt_mclk = 1;
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@@ -1031,9 +1031,9 @@ static void set_timing_cfg_5(fsl_ddr_cfg_regs_t *ddr)
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unsigned int wodt_off = 0; /* Write to ODT off */
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#if defined(CONFIG_FSL_DDR3)
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- rodt_on = 3; /* 2 clocks */
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+ rodt_on = 2; /* 2 clocks */
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rodt_off = 4; /* 4 clocks */
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- wodt_on = 2; /* 1 clocks */
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+ wodt_on = 1; /* 1 clocks */
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wodt_off = 4; /* 4 clocks */
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#endif
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@@ -1106,9 +1106,9 @@ static void set_ddr_wrlvl_cntl(fsl_ddr_cfg_regs_t *ddr, unsigned int wrlvl_en,
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/*
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* Write leveling repetition time
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* at least tWLO + 6 clocks clocks
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- * we set it 32
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+ * we set it 64
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*/
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- wrlvl_wlr = 0x5;
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+ wrlvl_wlr = 0x6;
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/*
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* Write leveling start time
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* The value use for the DQS_ADJUST for the first sample
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