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@@ -58,10 +58,9 @@ u32 is_mem_sdr(void)
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/*
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* make_cs1_contiguous -
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- * - For es2 and above remap cs1 behind cs0 to allow command line
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- * mem=xyz use all memory with out discontinuous support compiled in.
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- * Could do it at the ATAG, but there really is two banks...
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- * - Called as part of 2nd phase DDR init.
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+ * - When we have CS1 populated we want to have it mapped after cs0 to allow
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+ * command line mem=xyz use all memory with out discontinuous support
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+ * compiled in. We could do it in the ATAG, but there really is two banks...
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*/
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void make_cs1_contiguous(void)
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{
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@@ -207,16 +206,16 @@ int dram_init(void)
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size0 = get_sdr_cs_size(CS0);
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/*
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- * If a second bank of DDR is attached to CS1 this is
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- * where it can be started. Early init code will init
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- * memory on CS0.
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+ * We always need to have cs_cfg point at where the second
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+ * bank would be, if present. Failure to do so can lead to
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+ * strange situations where memory isn't detected and
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+ * configured correctly. CS0 will already have been setup
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+ * at this point.
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*/
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- if ((sysinfo.mtype == DDR_COMBO) || (sysinfo.mtype == DDR_STACKED)) {
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- do_sdrc_init(CS1, NOT_EARLY);
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- make_cs1_contiguous();
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+ make_cs1_contiguous();
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+ do_sdrc_init(CS1, NOT_EARLY);
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+ size1 = get_sdr_cs_size(CS1);
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- size1 = get_sdr_cs_size(CS1);
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- }
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gd->ram_size = size0 + size1;
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return 0;
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