enabled fastboot on vybrid

1.modified the incorrect anadig register setting.
2.enable USB function followed the instruction on RM.

Signed-off-by: Han Xu <b45815@freescale.com>

arch/arm/cpu/armv7/vf610/generic.c

@@ -331,9 +331,25 @@ void set_usboh3_clk(void)
 
 void set_usb_phy1_clk(void)
 {
+	struct ccm_reg *ccm = (struct ccm_reg *)CCM_BASE_ADDR;
 	struct anadig_reg *anadig = (struct anadig_reg *)ANADIG_BASE_ADDR;
     u32 reg;
+    /*setup clocking and PLL*/
+    reg = readl(&ccm->clpcr);
+    reg &= ~CCM_CLPCR_SBYOS_MASK;
+    writel(reg, &ccm->clpcr);
+
+    /*setup 3v0 regulator*/
+    reg = readl(&anadig->reg_3p0);
+    reg |= ANADIG_3P0_EN_BO_MASK;
+    reg |= ANADIG_3P0_EN_LINREG_MASK;
+    writel(reg, &anadig->reg_3p0);
+    while(!(readl(&anadig->reg_3p0)& ANADIG_3P0_OK_VDD3P0_MASK))
+
+
     reg = readl(&anadig->pll3_ctrl);
+    reg &= ~ANADIG_PLL3_CTRL_BYPASS_CLK_SRC;
+    reg &= ~ANADIG_PLL3_CTRL_BYPASS;
     reg |= ANADIG_PLL3_CTRL_POWERDOWN;
     reg |= ANADIG_PLL3_CTRL_ENUSBCLK;
     writel(reg, &anadig->pll3_ctrl);
@@ -342,21 +358,37 @@ void set_usb_phy1_clk(void)
 void enable_usboh3_clk(unsigned char enable)
 {
 	struct ccm_reg *ccm = (struct ccm_reg *)CCM_BASE_ADDR;
-        u32 reg;
-        reg = readl(&ccm->ccgr1);
-        if (enable)
-                reg |= CCM_CCGR1_USBC0_CTRL_MASK ;
-        else
-                reg &= ~CCM_CCGR1_USBC0_CTRL_MASK;
-        writel(reg, &ccm->ccgr1);
+	struct anadig_reg *anadig = (struct anadig_reg *)ANADIG_BASE_ADDR;
+    u32 reg;
+    reg = readl(&ccm->ccgr1);
+    if (enable)
+            reg |= CCM_CCGR1_USBC0_CTRL_MASK ;
+    else
+            reg &= ~CCM_CCGR1_USBC0_CTRL_MASK;
+    writel(reg, &ccm->ccgr1);
+
+    reg = readl(&anadig->pll3_ctrl);
+    reg &= ~ANADIG_PLL3_CTRL_BYPASS_CLK_SRC;
+    reg &= ~ANADIG_PLL3_CTRL_BYPASS;
+    reg |= ANADIG_PLL3_CTRL_POWERDOWN;
+    reg |= ANADIG_PLL3_CTRL_ENUSBCLK;
+    writel(reg, &anadig->pll3_ctrl);
 }
 
 void enable_usb_phy1_clk(unsigned char enable)
 {
-        if (enable) {
-                writel(BM_USBPHY_CTRL_CLKGATE, USB_PHY0_BASE_ADDR + HW_USBPHY_CTRL_CLR);
-        } else {
-                writel(BM_USBPHY_CTRL_CLKGATE, USB_PHY0_BASE_ADDR + HW_USBPHY_CTRL_SET);
-        }
+    u32 reg;
+    void* usb_reg = (void *)0x40035800;
+    if (enable) {
+        writel(BM_USBPHY_CTRL_SFTRST | BM_USBPHY_CTRL_CLKGATE, USB_PHY0_BASE_ADDR + HW_USBPHY_CTRL_CLR);
+        writel(BM_USBPHY_DEBUG_CLKGATE, USB_PHY0_BASE_ADDR + HW_USBPHY_DEBUG_CLR);
+        writel(BM_USBPHY_CTRL_ENUTMILEVEL3 | BM_USBPHY_CTRL_ENUTMILEVEL2, USB_PHY0_BASE_ADDR + HW_USBPHY_CTRL_SET);
+        writel(0, USB_PHY0_BASE_ADDR + HW_USBPHY_PWD);
+        reg = readl(&usb_reg);
+        reg |= 1<<9;
+        writel(reg, &usb_reg);
+    } else {
+        writel(BM_USBPHY_CTRL_CLKGATE, USB_PHY0_BASE_ADDR + HW_USBPHY_CTRL_SET);
+    }
 }
 

arch/arm/include/asm/arch-vf610/crm_regs.h

@@ -85,12 +85,13 @@ struct anadig_reg {
 	u32 pll4_num;
 	u32 resv7[3];
 	u32 pll4_denom;
+	u32 resv[3];
 	u32 pll6_ctrl;
 	u32 resv8[3];
 	u32 pll6_num;
 	u32 resv9[3];
 	u32 pll6_denom;
-	u32 resv10[3];
+	u32 resv10[7];
 	u32 pll5_ctrl;
 	u32 resv11[3];
 	u32 pll3_pfd;
@@ -176,6 +177,8 @@ struct anadig_reg {
 #define CCM_CSCMR2_RMII_CLK_SEL_MASK		(0x3 << 4)
 #define CCM_CSCMR2_RMII_CLK_SEL(v)		(((v) & 0x3) << 4)
 
+#define CCM_CLPCR_SBYOS_MASK            (0x1 << 6)
+
 #define CCM_REG_CTRL_MASK			0xffffffff
 #define CCM_CCGR0_UART1_CTRL_MASK		(0x3 << 16)
 #define CCM_CCGR1_USBC0_CTRL_MASK       (0x3 << 8)
@@ -197,8 +200,10 @@ struct anadig_reg {
 #define CCM_CCGR9_FEC0_CTRL_MASK		0x3
 #define CCM_CCGR9_FEC1_CTRL_MASK		(0x3 << 2)
 
-#define ANADIG_PLL3_CTRL_ENABLE			(1 << 13)
 #define ANADIG_PLL3_CTRL_POWERDOWN		(1 << 12)
+#define ANADIG_PLL3_CTRL_ENABLE			(1 << 13)
+#define ANADIG_PLL3_CTRL_BYPASS_CLK_SRC (1 << 14)
+#define ANADIG_PLL3_CTRL_BYPASS         (1 << 16)
 #define ANADIG_PLL3_CTRL_ENUSBCLK       (1 << 6)
 #define ANADIG_PLL2_CTRL_ENABLE			(1 << 13)
 #define ANADIG_PLL2_CTRL_POWERDOWN		(1 << 12)
@@ -206,6 +211,9 @@ struct anadig_reg {
 #define ANADIG_PLL1_CTRL_ENABLE			(1 << 13)
 #define ANADIG_PLL1_CTRL_POWERDOWN		(1 << 12)
 #define ANADIG_PLL1_CTRL_DIV_SELECT		1
+#define ANADIG_3P0_EN_LINREG_MASK       1
+#define ANADIG_3P0_EN_BO_MASK           (1 << 1)
+#define ANADIG_3P0_OK_VDD3P0_MASK       (1 << 17)
 
 #define FASE_CLK_FREQ		24000000
 #define SLOW_CLK_FREQ		32000

arch/arm/include/asm/arch-vf610/imx-regs.h

@@ -102,6 +102,8 @@
 #define ESDHC1_BASE_ADDR	(AIPS1_BASE_ADDR + 0x00032000)
 #define ENET_BASE_ADDR		(AIPS1_BASE_ADDR + 0x00050000)
 
+/*GPIO*/
+#define GPIO2_PSOR          (0x400FF084)
 /* MUX mode and PAD ctrl are in one register */
 #define CONFIG_IOMUX_SHARE_CONF_REG
 

arch/arm/include/asm/arch-vf610/iomux-vf610.h

@@ -31,6 +31,8 @@
 				PAD_CTL_OBE_IBE_ENABLE)
 #define VF610_DDR_PAD_CTRL	PAD_CTL_DSE_25ohm
 
+#define VF610_USB_PAD_CTRL	(PAD_CTL_PUS_100K_UP | \
+			PAD_CTL_DSE_50ohm | PAD_CTL_OBE_IBE_ENABLE)
 enum {
 	VF610_PAD_PTA6__RMII0_CLKIN		= IOMUX_PAD(0x0000, 0x0000, 2, __NA_, 0, VF610_ENET_PAD_CTRL),
 	VF610_PAD_PTB4__UART1_TX		= IOMUX_PAD(0x0068, 0x0068, 2, 0x0380, 0, VF610_UART_PAD_CTRL),
@@ -96,6 +98,8 @@ enum {
 	VF610_PAD_DDR_WE__DDR_WE_B		= IOMUX_PAD(0x02d0, 0x02d0, 0, __NA_, 0, VF610_DDR_PAD_CTRL),
 	VF610_PAD_DDR_ODT1__DDR_ODT_0		= IOMUX_PAD(0x02d4, 0x02d4, 0, __NA_, 0, VF610_DDR_PAD_CTRL),
 	VF610_PAD_DDR_ODT0__DDR_ODT_1		= IOMUX_PAD(0x02d8, 0x02d8, 0, __NA_, 0, VF610_DDR_PAD_CTRL),
+	VF610_PAD_PTD6__GPIO85              = IOMUX_PAD(0x0154, 0x0154, 0, __NA_, 0, VF610_USB_PAD_CTRL),
+	VF610_PAD_PTD13__GPIO92             = IOMUX_PAD(0x0170, 0x0170, 0, __NA_, 0, VF610_DDR_PAD_CTRL),
 };
 
 #endif	/* __IOMUX_VF610_H__ */

board/freescale/vf610twr/vf610twr.c

@@ -43,6 +43,9 @@ DECLARE_GLOBAL_DATA_PTR;
 #define ENET_PAD_CTRL	(PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_HIGH | \
 			PAD_CTL_DSE_50ohm | PAD_CTL_OBE_IBE_ENABLE)
 
+#define USB_PAD_CTRL	(PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED| \
+			PAD_CTL_DSE_50ohm | PAD_CTL_OBE_IBE_ENABLE)
+
 void setup_iomux_ddr(void)
 {
 	static const iomux_v3_cfg_t ddr_pads[] = {
@@ -414,17 +417,19 @@ int checkboard(void)
 
 void udc_pins_setting(void)
 {
-        //imx_iomux_v3_setup_pad(MX6X_IOMUX(PAD_ENET_RX_ER__ANATOP_USBOTG_ID));
-        //imx_iomux_v3_setup_pad(MX6X_IOMUX(PAD_EIM_D22__GPIO_3_22));
-        //imx_iomux_v3_setup_pad(MX6X_IOMUX(PAD_ENET_TXD1__GPIO_1_29));
-
-        /* USB_OTG_PWR = 0 */
-        //gpio_direction_output(USB_OTG_PWR, 0);
-        /* USB_H1_POWER = 1 */
-        //gpio_direction_output(USB_H1_POWER, 1);
-
-        //imx_iomux_set_gpr_register(1, 13, 1, 0);
+    u32 reg;
+    void *gpio_reg = (void *)GPIO2_PSOR;
+	static const iomux_v3_cfg_t usb0_pads[] = {
+		NEW_PAD_CTRL(VF610_PAD_PTD6__GPIO85, USB_PAD_CTRL),
+		NEW_PAD_CTRL(VF610_PAD_PTD13__GPIO92, USB_PAD_CTRL),
+	};
 
+	imx_iomux_v3_setup_multiple_pads(usb0_pads, ARRAY_SIZE(usb0_pads));
+    /*set PTD6 and PTD13*/
+    reg = readl(GPIO2_PSOR);
+    reg |= (1<<21);
+    reg |= (1<<28);
+    writel(0x10200000, &gpio_reg);
 }
 #endif
 

drivers/fastboot/fastboot.c

@@ -107,23 +107,23 @@ static struct usb_string_descriptor *fastboot_string_table[STR_COUNT];
 static u8 wstrLang[4] = {4, USB_DT_STRING, 0x9, 0x4};
 static union {
     u16 __dummy;
-    u8 _wstrManufacturer[2 + 2 * (sizeof(CONFIG_FASTBOOT_MANUFACTURER_STR))];
+    u8 _wstrManufacturer[2 * (sizeof(CONFIG_FASTBOOT_MANUFACTURER_STR))];
 } wstrManufacturer;
 static union {
     u16 __dummy;
-    u8 _wstrProduct[2 + 2 * (sizeof(CONFIG_FASTBOOT_PRODUCT_NAME_STR))];
+    u8 _wstrProduct[2 * (sizeof(CONFIG_FASTBOOT_PRODUCT_NAME_STR))];
 } wstrProduct;
 static union {
     u16 __dummy;
-    u8 _wstrSerial[2 + 2*(sizeof(CONFIG_FASTBOOT_SERIAL_NUM))];
+    u8 _wstrSerial[2*(sizeof(CONFIG_FASTBOOT_SERIAL_NUM))];
 } wstrSerial;
 static union {
     u16 __dummy;
-    u8 _wstrConfiguration[2 + 2 * (sizeof(CONFIG_FASTBOOT_CONFIGURATION_STR))];
+    u8 _wstrConfiguration[2 * (sizeof(CONFIG_FASTBOOT_CONFIGURATION_STR))];
 } wstrConfiguration;
 static union {
     u16 __dummy;
-    u8 _wstrDataInterface[2 + 2 * (sizeof(CONFIG_FASTBOOT_INTERFACE_STR))];
+    u8 _wstrDataInterface[2 * (sizeof(CONFIG_FASTBOOT_INTERFACE_STR))];
 } wstrDataInterface;
 
 /* Standard USB Data Structures */

drivers/usb/gadget/imx_udc.c

@@ -755,6 +755,8 @@ static int ll;
 void mxc_irq_poll(void)
 {
 	unsigned irq_src = readl(USB_USBSTS) & readl(USB_USBINTR);
+    if (irq_src != 0)
+        printf("irq_src %8x\n", irq_src);
 	writel(irq_src, USB_USBSTS);
 
 	if (irq_src == 0)
@@ -809,8 +811,8 @@ void udc_disable_over_current(void)
  */
 int mxc_udc_init(void)
 {
-	set_usboh3_clk();
 	set_usb_phy1_clk();
+	set_usboh3_clk();
 	enable_usboh3_clk(1);
 #if defined(CONFIG_MX6Q) || defined(CONFIG_MX6DL) || defined(CONFIG_MX6SL)
 	udc_disable_over_current();