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@@ -58,13 +58,15 @@ static struct flash_dev flash_ids[] = {
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*
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*
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* Wait until TFF is set in status register
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* Wait until TFF is set in status register
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*/
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*/
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-static void smi_wait_xfer_finish(int timeout)
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+static int smi_wait_xfer_finish(int timeout)
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{
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{
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- while (timeout--) {
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+ do {
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if (readl(&smicntl->smi_sr) & TFF)
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if (readl(&smicntl->smi_sr) & TFF)
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- break;
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+ return 0;
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udelay(1000);
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udelay(1000);
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- }
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+ } while (timeout--);
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+
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+ return -1;
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}
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}
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/*
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/*
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@@ -83,7 +85,8 @@ static unsigned int smi_read_id(flash_info_t *info, int banknum)
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writel((banknum << BANKSEL_SHIFT) | SEND | TX_LEN_1 | RX_LEN_3,
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writel((banknum << BANKSEL_SHIFT) | SEND | TX_LEN_1 | RX_LEN_3,
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&smicntl->smi_cr2);
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&smicntl->smi_cr2);
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- smi_wait_xfer_finish(XFER_FINISH_TOUT);
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+ if (smi_wait_xfer_finish(XFER_FINISH_TOUT))
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+ return -EIO;
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value = (readl(&smicntl->smi_rr) & 0x00FFFFFF);
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value = (readl(&smicntl->smi_rr) & 0x00FFFFFF);
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@@ -151,7 +154,8 @@ static unsigned int smi_read_sr(int bank)
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/* Performing a RSR instruction in HW mode */
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/* Performing a RSR instruction in HW mode */
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writel((bank << BANKSEL_SHIFT) | RD_STATUS_REG, &smicntl->smi_cr2);
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writel((bank << BANKSEL_SHIFT) | RD_STATUS_REG, &smicntl->smi_cr2);
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- smi_wait_xfer_finish(XFER_FINISH_TOUT);
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+ if (smi_wait_xfer_finish(XFER_FINISH_TOUT))
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+ return -1;
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/* Restore the CTRL REG1 state */
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/* Restore the CTRL REG1 state */
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writel(ctrlreg1, &smicntl->smi_cr1);
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writel(ctrlreg1, &smicntl->smi_cr1);
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@@ -211,7 +215,8 @@ static int smi_write_enable(int bank)
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/* Give the Flash, Write Enable command */
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/* Give the Flash, Write Enable command */
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writel((bank << BANKSEL_SHIFT) | WE, &smicntl->smi_cr2);
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writel((bank << BANKSEL_SHIFT) | WE, &smicntl->smi_cr2);
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- smi_wait_xfer_finish(XFER_FINISH_TOUT);
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+ if (smi_wait_xfer_finish(XFER_FINISH_TOUT))
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+ return -1;
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/* Restore the CTRL REG1 state */
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/* Restore the CTRL REG1 state */
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writel(ctrlreg1, &smicntl->smi_cr1);
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writel(ctrlreg1, &smicntl->smi_cr1);
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@@ -292,7 +297,8 @@ static int smi_sector_erase(flash_info_t *info, unsigned int sector)
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writel(instruction, &smicntl->smi_tr);
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writel(instruction, &smicntl->smi_tr);
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writel((bank << BANKSEL_SHIFT) | SEND | TX_LEN_4,
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writel((bank << BANKSEL_SHIFT) | SEND | TX_LEN_4,
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&smicntl->smi_cr2);
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&smicntl->smi_cr2);
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- smi_wait_xfer_finish(XFER_FINISH_TOUT);
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+ if (smi_wait_xfer_finish(XFER_FINISH_TOUT))
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+ return -EIO;
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if (smi_wait_till_ready(bank, CONFIG_SYS_FLASH_ERASE_TOUT))
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if (smi_wait_till_ready(bank, CONFIG_SYS_FLASH_ERASE_TOUT))
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return -EBUSY;
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return -EBUSY;
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