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@@ -2,6 +2,9 @@
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* (C) Copyright 2006
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* Heiko Schocher, DENX Software Engineering, hs@denx.de
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*
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+ * (C) Copyright 2006
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+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
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+ *
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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@@ -22,69 +25,27 @@
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*/
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#include <common.h>
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-#include <asm/io.h>
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#if (CONFIG_COMMANDS & CFG_CMD_NAND)
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+#include <asm/processor.h>
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#include <nand.h>
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-#if 0
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-#define HS_printf(fmt,arg...) \
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- printf("HS %s %s: " fmt,__FILE__, __FUNCTION__, ##arg)
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-#else
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-#define HS_printf(fmt,arg...) \
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- do { } while (0)
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-#endif
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-
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-#if 0
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-#define CPLD_REG uchar
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-#else
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-#define CPLD_REG u16
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-#endif
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-
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struct alpr_ndfc_regs {
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- CPLD_REG cmd[4];
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- CPLD_REG addr_wait;
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- CPLD_REG term;
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- CPLD_REG dummy;
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- uchar dum2[2];
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- CPLD_REG data;
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+ u16 cmd[4];
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+ u16 addr_wait;
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+ u16 term;
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+ u16 dummy;
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+ u16 dummy2;
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+ u16 data;
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};
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static u8 hwctl;
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-static struct alpr_ndfc_regs *alpr_ndfc;
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-static int alpr_chip = 0;
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+static struct alpr_ndfc_regs *alpr_ndfc = NULL;
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-#if 1
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-static int pdnb3_nand_dev_ready(struct mtd_info *mtd);
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+#define readb(addr) (u8)(*(volatile u16 *)(addr))
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+#define writeb(d,addr) *(volatile u16 *)(addr) = ((u16)(d))
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-#if 1
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-static u_char alpr_read (void *padr) {
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- return (u_char )*((u16 *)(padr));
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-}
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-#else
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-static u_char alpr_read (void *padr) {
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- u16 hilf;
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- u_char ret = 0;
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- hilf = *((u16 *)(padr));
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- ret = hilf;
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-printf("%p hilf: %x ret: %x\n", padr, hilf, ret);
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- return ret;
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-}
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-#endif
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-
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-static void alpr_write (u_char byte, void *padr) {
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-HS_printf("%p Byte: %x\n", padr, byte);
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- *(volatile u16 *)padr = (u16)(byte);
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-}
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-
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-#elif 0
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-#define alpr_read(a) (*(volatile u16 *) (a))
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-#define alpr_write(a, b) ((*(volatile u16 *) (a)) = (b))
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-#else
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-#define alpr_read(a) readw(a)
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-#define alpr_write(a, b) writew(a, b)
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-#endif
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/*
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* The ALPR has a NAND Flash Controller (NDFC) that handles all accesses to
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* the NAND devices. The NDFC has command, address and data registers that
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@@ -93,11 +54,10 @@ HS_printf("%p Byte: %x\n", padr, byte);
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* We can then use this information in the read and write functions to
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* determine which NDFC register to access.
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*
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- * There are 2 NAND devices on the board, a Hynix HY27US08561A (32 MByte).
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+ * There are 2 NAND devices on the board, a Hynix HY27US08561A (1 GByte).
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*/
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-static void pdnb3_nand_hwcontrol(struct mtd_info *mtd, int cmd)
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+static void alpr_nand_hwcontrol(struct mtd_info *mtd, int cmd)
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{
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-HS_printf("cmd: %x\n", cmd);
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switch (cmd) {
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case NAND_CTL_SETCLE:
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hwctl |= 0x1;
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@@ -114,136 +74,84 @@ HS_printf("cmd: %x\n", cmd);
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case NAND_CTL_SETNCE:
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break;
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case NAND_CTL_CLRNCE:
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- alpr_write(0x00, &(alpr_ndfc->term));
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+ writeb(0x00, &(alpr_ndfc->term));
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break;
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}
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}
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-static void pdnb3_nand_write_byte(struct mtd_info *mtd, u_char byte)
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+static void alpr_nand_write_byte(struct mtd_info *mtd, u_char byte)
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{
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-HS_printf("hwctl: %x %x %x %x\n", hwctl, byte, &(alpr_ndfc->cmd[alpr_chip]), &(alpr_ndfc->addr_wait));
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+ struct nand_chip *nand = mtd->priv;
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+
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if (hwctl & 0x1)
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- alpr_write(byte, &(alpr_ndfc->cmd[alpr_chip]));
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+ /*
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+ * IO_ADDR_W used as CMD[i] reg to support multiple NAND
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+ * chips.
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+ */
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+ writeb(byte, nand->IO_ADDR_W);
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else if (hwctl & 0x2) {
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- alpr_write(byte, &(alpr_ndfc->addr_wait));
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+ writeb(byte, &(alpr_ndfc->addr_wait));
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} else
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- alpr_write(byte, &(alpr_ndfc->data));
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+ writeb(byte, &(alpr_ndfc->data));
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}
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-static u_char pdnb3_nand_read_byte(struct mtd_info *mtd)
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+static u_char alpr_nand_read_byte(struct mtd_info *mtd)
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{
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- return alpr_read(&(alpr_ndfc->data));
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+ return readb(&(alpr_ndfc->data));
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}
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-static void pdnb3_nand_write_buf(struct mtd_info *mtd, const u_char *buf, int len)
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+static void alpr_nand_write_buf(struct mtd_info *mtd, const u_char *buf, int len)
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{
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+ struct nand_chip *nand = mtd->priv;
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int i;
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-/*printf("%s chip:%d hwctl:%x size:%d\n", __FUNCTION__, alpr_chip, hwctl, len);*/
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for (i = 0; i < len; i++) {
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if (hwctl & 0x1)
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- alpr_write(buf[i], &(alpr_ndfc->cmd[alpr_chip]));
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- else if (hwctl & 0x2) {
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- alpr_write(buf[i], &(alpr_ndfc->addr_wait));
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- } else {
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- alpr_write(buf[i], &(alpr_ndfc->data));
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- /*printf("i: %d\n", i);*/
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- }
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+ /*
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+ * IO_ADDR_W used as CMD[i] reg to support multiple NAND
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+ * chips.
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+ */
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+ writeb(buf[i], nand->IO_ADDR_W);
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+ else if (hwctl & 0x2)
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+ writeb(buf[i], &(alpr_ndfc->addr_wait));
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+ else
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+ writeb(buf[i], &(alpr_ndfc->data));
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}
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}
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-static void pdnb3_nand_read_buf(struct mtd_info *mtd, u_char *buf, int len)
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+static void alpr_nand_read_buf(struct mtd_info *mtd, u_char *buf, int len)
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{
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int i;
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for (i = 0; i < len; i++) {
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- buf[i] = alpr_read(&(alpr_ndfc->data));
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+ buf[i] = readb(&(alpr_ndfc->data));
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}
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}
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-static int pdnb3_nand_verify_buf(struct mtd_info *mtd, const u_char *buf, int len)
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+static int alpr_nand_verify_buf(struct mtd_info *mtd, const u_char *buf, int len)
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{
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int i;
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for (i = 0; i < len; i++)
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- if (buf[i] != alpr_read(&(alpr_ndfc->data)))
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+ if (buf[i] != readb(&(alpr_ndfc->data)))
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return i;
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return 0;
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}
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-static int pdnb3_nand_dev_ready(struct mtd_info *mtd)
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+static int alpr_nand_dev_ready(struct mtd_info *mtd)
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{
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-#if 1
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volatile u_char val;
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-/*printf("%s aufruf\n", __FUNCTION__);*/
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/*
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* Blocking read to wait for NAND to be ready
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*/
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- val = alpr_read(&(alpr_ndfc->addr_wait));
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+ val = readb(&(alpr_ndfc->addr_wait));
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/*
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* Return always true
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*/
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return 1;
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-#else
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- u8 hwctl_org = hwctl;
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- unsigned long timeo;
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- u8 val;
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-
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- hwctl = 0x01;
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- pdnb3_nand_write_byte (mtd, NAND_CMD_STATUS);
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- hwctl = hwctl_org;
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-
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- reset_timer();
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- while (1) {
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- if (get_timer(0) > timeo) {
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- printf("Timeout!");
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- return 0;
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- }
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-
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-val = pdnb3_nand_read_byte(mtd);
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-/*printf("%s val: %x\n", __FUNCTION__, val);*/
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- if (val & NAND_STATUS_READY)
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- break;
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- }
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- return 1;
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-#endif
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-
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-}
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-
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-static void alpr_select_chip(struct mtd_info *mtd, int chip)
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-{
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- alpr_chip = chip;
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-}
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-
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-static int alpr_nand_wait(struct mtd_info *mtd, struct nand_chip *this, int state)
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-{
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- unsigned long timeo;
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-
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- if (state == FL_ERASING)
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- timeo = CFG_HZ * 400;
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- else
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- timeo = CFG_HZ * 20;
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-
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- if ((state == FL_ERASING) && (this->options & NAND_IS_AND))
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- this->cmdfunc(mtd, NAND_CMD_STATUS_MULTI, -1, -1);
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- else
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- this->cmdfunc(mtd, NAND_CMD_STATUS, -1, -1);
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-
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- reset_timer();
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-
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- while (1) {
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- if (get_timer(0) > timeo) {
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- printf("Timeout!");
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- return 0;
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- }
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-
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- if (this->read_byte(mtd) & NAND_STATUS_READY)
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- break;
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- }
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- return this->read_byte(mtd);
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}
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void board_nand_init(struct nand_chip *nand)
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@@ -252,20 +160,14 @@ void board_nand_init(struct nand_chip *nand)
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nand->eccmode = NAND_ECC_SOFT;
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- /* Set address of NAND IO lines (Using Linear Data Access Region) */
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- nand->IO_ADDR_R = (void __iomem *) ((ulong) alpr_ndfc + 0x10);
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- nand->IO_ADDR_W = (void __iomem *) ((ulong) alpr_ndfc + 0x10);
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/* Reference hardware control function */
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- nand->hwcontrol = pdnb3_nand_hwcontrol;
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+ nand->hwcontrol = alpr_nand_hwcontrol;
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/* Set command delay time */
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- nand->hwcontrol = pdnb3_nand_hwcontrol;
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- nand->write_byte = pdnb3_nand_write_byte;
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- nand->read_byte = pdnb3_nand_read_byte;
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- nand->write_buf = pdnb3_nand_write_buf;
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- nand->read_buf = pdnb3_nand_read_buf;
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- nand->verify_buf = pdnb3_nand_verify_buf;
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- nand->dev_ready = pdnb3_nand_dev_ready;
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- nand->select_chip = alpr_select_chip;
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- nand->waitfunc = alpr_nand_wait;
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+ nand->write_byte = alpr_nand_write_byte;
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+ nand->read_byte = alpr_nand_read_byte;
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+ nand->write_buf = alpr_nand_write_buf;
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+ nand->read_buf = alpr_nand_read_buf;
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+ nand->verify_buf = alpr_nand_verify_buf;
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+ nand->dev_ready = alpr_nand_dev_ready;
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}
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#endif
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Stefan Roese