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@@ -65,6 +65,7 @@ sdram_conf_t ddr_cs_conf[] = {
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#define N_DDR_CS_CONF (sizeof(ddr_cs_conf) / sizeof(ddr_cs_conf[0]))
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#define N_DDR_CS_CONF (sizeof(ddr_cs_conf) / sizeof(ddr_cs_conf[0]))
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int cas_latency (void);
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int cas_latency (void);
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+static phys_size_t sdram_setup(int);
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/*
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/*
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* Autodetect onboard DDR SDRAM on 85xx platforms
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* Autodetect onboard DDR SDRAM on 85xx platforms
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@@ -73,7 +74,26 @@ int cas_latency (void);
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* so this should be extended for other future boards
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* so this should be extended for other future boards
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* using this routine!
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* using this routine!
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*/
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*/
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-long int sdram_setup (int casl)
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+phys_size_t fixed_sdram(void)
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+{
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+ int casl = 0;
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+ phys_size_t dram_size = 0;
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+
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+ casl = cas_latency();
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+ dram_size = sdram_setup(casl);
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+ if ((dram_size == 0) && (casl != CONFIG_DDR_DEFAULT_CL)) {
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+ /*
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+ * Try again with default CAS latency
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+ */
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+ printf("Problem with CAS lantency, using default CL %d/10!\n",
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+ CONFIG_DDR_DEFAULT_CL);
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+ dram_size = sdram_setup(CONFIG_DDR_DEFAULT_CL);
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+ puts(" ");
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+ }
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+ return dram_size;
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+}
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+
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+static phys_size_t sdram_setup(int casl)
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{
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{
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int i;
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int i;
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volatile ccsr_ddr_t *ddr = (void *)(CONFIG_SYS_MPC85xx_DDR_ADDR);
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volatile ccsr_ddr_t *ddr = (void *)(CONFIG_SYS_MPC85xx_DDR_ADDR);
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@@ -376,8 +396,7 @@ long int sdram_setup (int casl)
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phys_size_t initdram (int board_type)
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phys_size_t initdram (int board_type)
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{
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{
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- long dram_size = 0;
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- int casl;
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+ phys_size_t dram_size = 0;
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#if defined(CONFIG_DDR_DLL)
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#if defined(CONFIG_DDR_DLL)
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/*
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/*
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@@ -407,17 +426,7 @@ phys_size_t initdram (int board_type)
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}
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}
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#endif
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#endif
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- casl = cas_latency ();
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- dram_size = sdram_setup (casl);
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- if ((dram_size == 0) && (casl != CONFIG_DDR_DEFAULT_CL)) {
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- /*
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- * Try again with default CAS latency
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- */
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- printf ("Problem with CAS lantency, using default CL %d/10!\n",
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- CONFIG_DDR_DEFAULT_CL);
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- dram_size = sdram_setup (CONFIG_DDR_DEFAULT_CL);
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- puts (" ");
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- }
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+ dram_size = fixed_sdram();
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return dram_size;
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return dram_size;
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}
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}
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