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@@ -270,9 +270,16 @@ static int mmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd,
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__func__, mask);
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return -1;
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} else if (mask & TEGRA_MMC_NORINTSTS_DMA_INTERRUPT) {
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- /* DMA Interrupt */
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+ /*
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+ * DMA Interrupt, restart the transfer where
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+ * it was interrupted.
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+ */
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+ unsigned int address = readl(&host->reg->sysad);
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+
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debug("DMA end\n");
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- break;
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+ writel(TEGRA_MMC_NORINTSTS_DMA_INTERRUPT,
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+ &host->reg->norintsts);
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+ writel(address, &host->reg->sysad);
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} else if (mask & TEGRA_MMC_NORINTSTS_XFER_COMPLETE) {
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/* Transfer Complete */
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debug("r/w is done\n");
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@@ -419,6 +426,7 @@ static int mmc_core_init(struct mmc *mmc)
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* NORMAL Interrupt Status Enable Register init
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* [5] ENSTABUFRDRDY : Buffer Read Ready Status Enable
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* [4] ENSTABUFWTRDY : Buffer write Ready Status Enable
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+ * [3] ENSTADMAINT : DMA boundary interrupt
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* [1] ENSTASTANSCMPLT : Transfre Complete Status Enable
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* [0] ENSTACMDCMPLT : Command Complete Status Enable
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*/
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@@ -426,6 +434,7 @@ static int mmc_core_init(struct mmc *mmc)
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mask &= ~(0xffff);
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mask |= (TEGRA_MMC_NORINTSTSEN_CMD_COMPLETE |
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TEGRA_MMC_NORINTSTSEN_XFER_COMPLETE |
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+ TEGRA_MMC_NORINTSTSEN_DMA_INTERRUPT |
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TEGRA_MMC_NORINTSTSEN_BUFFER_WRITE_READY |
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TEGRA_MMC_NORINTSTSEN_BUFFER_READ_READY);
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writel(mask, &host->reg->norintstsen);
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