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@@ -27,9 +27,9 @@
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#define pSYSCR ((uint16_t volatile *)SYSCR) /* System Configuration Register */
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#define pSYSCR ((uint16_t volatile *)SYSCR) /* System Configuration Register */
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#define bfin_read_SYSCR() bfin_read16(SYSCR)
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#define bfin_read_SYSCR() bfin_read16(SYSCR)
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#define bfin_write_SYSCR(val) bfin_write16(SYSCR, val)
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#define bfin_write_SYSCR(val) bfin_write16(SYSCR, val)
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-#define pSIC_RVECT ((uint32_t volatile *)SIC_RVECT) /* Interrupt Reset Vector Address Register */
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-#define bfin_read_SIC_RVECT() bfin_read32(SIC_RVECT)
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-#define bfin_write_SIC_RVECT(val) bfin_write32(SIC_RVECT, val)
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+#define pSIC_RVECT ((uint16_t volatile *)SIC_RVECT) /* Interrupt Reset Vector Address Register */
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+#define bfin_read_SIC_RVECT() bfin_read16(SIC_RVECT)
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+#define bfin_write_SIC_RVECT(val) bfin_write16(SIC_RVECT, val)
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#define pSIC_IMASK ((uint32_t volatile *)SIC_IMASK) /* Interrupt Mask Register */
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#define pSIC_IMASK ((uint32_t volatile *)SIC_IMASK) /* Interrupt Mask Register */
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#define bfin_read_SIC_IMASK() bfin_read32(SIC_IMASK)
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#define bfin_read_SIC_IMASK() bfin_read32(SIC_IMASK)
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#define bfin_write_SIC_IMASK(val) bfin_write32(SIC_IMASK, val)
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#define bfin_write_SIC_IMASK(val) bfin_write32(SIC_IMASK, val)
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