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@@ -319,7 +319,7 @@ enum EESR_BIT {
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EESR_FTC = 0x00200000, EESR_TDE = 0x00100000,
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EESR_TFE = 0x00080000, EESR_FRC = 0x00040000,
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EESR_RDE = 0x00020000, EESR_RFE = 0x00010000,
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-#if defined(CONFIG_CPU_SH7724) && !defined(CONFIG_CPU_SH7757)
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+#if defined(CONFIG_CPU_SH7724) || defined(CONFIG_CPU_SH7757)
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EESR_CND = 0x00000800,
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#endif
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EESR_DLC = 0x00000400,
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@@ -426,9 +426,7 @@ enum FELIC_MODE_BIT {
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#if defined(CONFIG_CPU_SH7763) || defined(CONFIG_CPU_SH7734)
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#define ECMR_CHG_DM (ECMR_TRCCM | ECMR_RZPF | ECMR_ZPF | ECMR_PFR | ECMR_RXF | \
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ECMR_TXF | ECMR_MCT)
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-#elif CONFIG_CPU_SH7757
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-#define ECMR_CHG_DM (ECMR_ZPF)
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-#elif CONFIG_CPU_SH7724
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+#elif CONFIG_CPU_SH7724 || CONFIG_CPU_SH7757
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#define ECMR_CHG_DM (ECMR_ZPF | ECMR_PFR | ECMR_RXF | ECMR_TXF)
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#else
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#define ECMR_CHG_DM (ECMR_ZPF | ECMR_PFR | ECMR_RXF | ECMR_TXF | ECMR_MCT)
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@@ -473,20 +471,12 @@ enum ECSIPR_STATUS_MASK_BIT {
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/* APR */
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enum APR_BIT {
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-#ifdef CONFIG_CPU_SH7757
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- APR_AP = 0x00000001,
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-#else
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APR_AP = 0x00000004,
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-#endif
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};
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/* MPR */
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enum MPR_BIT {
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-#ifdef CONFIG_CPU_SH7757
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- MPR_MP = 0x00000001,
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-#else
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MPR_MP = 0x00000006,
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-#endif
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};
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/* TRSCER */
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