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@@ -47,6 +47,7 @@ phys_size_t initdram (int board_type) {
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MCF_GPIO_SDRAM_SDWE | MCF_GPIO_SDRAM_SCAS |
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MCF_GPIO_SDRAM_SDWE | MCF_GPIO_SDRAM_SCAS |
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MCF_GPIO_SDRAM_SRAS | MCF_GPIO_SDRAM_SCKE |
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MCF_GPIO_SDRAM_SRAS | MCF_GPIO_SDRAM_SCKE |
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MCF_GPIO_SDRAM_SDCS_11);
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MCF_GPIO_SDRAM_SDCS_11);
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+ asm(" nop");
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/*
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/*
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* Check to see if the SDRAM has already been initialized
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* Check to see if the SDRAM has already been initialized
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@@ -55,8 +56,9 @@ phys_size_t initdram (int board_type) {
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if (!(mbar_readLong(MCF_SDRAMC_DACR0) & MCF_SDRAMC_DACRn_RE)) {
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if (!(mbar_readLong(MCF_SDRAMC_DACR0) & MCF_SDRAMC_DACRn_RE)) {
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/* Initialize DRAM Control Register: DCR */
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/* Initialize DRAM Control Register: DCR */
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mbar_writeShort(MCF_SDRAMC_DCR,
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mbar_writeShort(MCF_SDRAMC_DCR,
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- MCF_SDRAMC_DCR_RTIM(0x01)
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- | MCF_SDRAMC_DCR_RC(0x30));
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+ MCF_SDRAMC_DCR_RTIM(2)
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+ | MCF_SDRAMC_DCR_RC(0x2E));
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+ asm(" nop");
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/*
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/*
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* Initialize DACR0
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* Initialize DACR0
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@@ -70,15 +72,18 @@ phys_size_t initdram (int board_type) {
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| MCF_SDRAMC_DACRn_CASL(1)
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| MCF_SDRAMC_DACRn_CASL(1)
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| MCF_SDRAMC_DACRn_CBM(3)
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| MCF_SDRAMC_DACRn_CBM(3)
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| MCF_SDRAMC_DACRn_PS(0));
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| MCF_SDRAMC_DACRn_PS(0));
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+ asm(" nop");
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/* Initialize DMR0 */
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/* Initialize DMR0 */
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mbar_writeLong(MCF_SDRAMC_DMR0,
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mbar_writeLong(MCF_SDRAMC_DMR0,
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MCF_SDRAMC_DMRn_BAM_16M
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MCF_SDRAMC_DMRn_BAM_16M
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| MCF_SDRAMC_DMRn_V);
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| MCF_SDRAMC_DMRn_V);
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+ asm(" nop");
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/* Set IP bit in DACR */
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/* Set IP bit in DACR */
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mbar_writeLong(MCF_SDRAMC_DACR0, mbar_readLong(MCF_SDRAMC_DACR0)
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mbar_writeLong(MCF_SDRAMC_DACR0, mbar_readLong(MCF_SDRAMC_DACR0)
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| MCF_SDRAMC_DACRn_IP);
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| MCF_SDRAMC_DACRn_IP);
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+ asm(" nop");
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/* Wait at least 20ns to allow banks to precharge */
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/* Wait at least 20ns to allow banks to precharge */
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for (i = 0; i < 5; i++)
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for (i = 0; i < 5; i++)
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@@ -86,6 +91,7 @@ phys_size_t initdram (int board_type) {
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/* Write to this block to initiate precharge */
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/* Write to this block to initiate precharge */
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*(u32 *)(CONFIG_SYS_SDRAM_BASE) = 0xa5a5a5a5;
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*(u32 *)(CONFIG_SYS_SDRAM_BASE) = 0xa5a5a5a5;
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+ asm(" nop");
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/* Set RE bit in DACR */
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/* Set RE bit in DACR */
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mbar_writeLong(MCF_SDRAMC_DACR0, mbar_readLong(MCF_SDRAMC_DACR0)
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mbar_writeLong(MCF_SDRAMC_DACR0, mbar_readLong(MCF_SDRAMC_DACR0)
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@@ -98,6 +104,7 @@ phys_size_t initdram (int board_type) {
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/* Finish the configuration by issuing the MRS */
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/* Finish the configuration by issuing the MRS */
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mbar_writeLong(MCF_SDRAMC_DACR0, mbar_readLong(MCF_SDRAMC_DACR0)
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mbar_writeLong(MCF_SDRAMC_DACR0, mbar_readLong(MCF_SDRAMC_DACR0)
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| MCF_SDRAMC_DACRn_MRS);
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| MCF_SDRAMC_DACRn_MRS);
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+ asm(" nop");
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/*
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/*
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* Write to the SDRAM Mode Register A0-A11 = 0x400
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* Write to the SDRAM Mode Register A0-A11 = 0x400
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@@ -109,6 +116,7 @@ phys_size_t initdram (int board_type) {
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* Burst Length = 1
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* Burst Length = 1
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*/
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*/
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*(u32 *)(CONFIG_SYS_SDRAM_BASE + 0x400) = 0xa5a5a5a5;
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*(u32 *)(CONFIG_SYS_SDRAM_BASE + 0x400) = 0xa5a5a5a5;
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+ asm(" nop");
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}
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}
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return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
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return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
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