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@@ -65,11 +65,9 @@ au_image_t au_image[] = {
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int N_AU_IMAGES = (sizeof(au_image) / sizeof(au_image[0]));
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-
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/* Prototypes */
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int gunzip(void *, int, unsigned char *, unsigned long *);
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-
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int board_early_init_f (void)
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{
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/*
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@@ -89,24 +87,18 @@ int board_early_init_f (void)
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mtdcr(uiccr, 0x00000000); /* set all to be non-critical*/
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mtdcr(uicpr, 0xFFFFFF99); /* set int polarities */
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mtdcr(uictr, 0x10000000); /* set int trigger levels */
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- mtdcr(uicvcr, 0x00000001); /* set vect base=0,INT0 highest priority*/
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+ mtdcr(uicvcr, 0x00000001); /* set vect base=0,INT0 highest prio */
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mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
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/*
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- * EBC Configuration Register: set ready timeout to 512 ebc-clks -> ca. 15 us
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+ * EBC Configuration Register: set ready timeout to
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+ * 512 ebc-clks -> ca. 15 us
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*/
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mtebc (epcr, 0xa8400000); /* ebc always driven */
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return 0;
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}
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-
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-int misc_init_f (void)
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-{
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- return 0; /* dummy implementation */
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-}
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-
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-
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int misc_init_r (void)
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{
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unsigned char *duart0_mcr = (unsigned char *)((ulong)DUART0_BA + 4);
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@@ -132,13 +124,16 @@ int misc_init_r (void)
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printf("\nFPGA: Booting failed ");
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switch (status) {
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case ERROR_FPGA_PRG_INIT_LOW:
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- printf("(Timeout: INIT not low after asserting PROGRAM*)\n ");
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+ printf("(Timeout: INIT not low "
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+ "after asserting PROGRAM*)\n");
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break;
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case ERROR_FPGA_PRG_INIT_HIGH:
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- printf("(Timeout: INIT not high after deasserting PROGRAM*)\n ");
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+ printf("(Timeout: INIT not high "
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+ "after deasserting PROGRAM*)\n");
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break;
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case ERROR_FPGA_PRG_DONE:
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- printf("(Timeout: DONE not high after programming FPGA)\n ");
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+ printf("(Timeout: DONE not high "
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+ "after programming FPGA)\n");
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break;
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}
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@@ -184,15 +179,16 @@ int misc_init_r (void)
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/*
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* Reset external DUARTs
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*/
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- out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) | CFG_DUART_RST); /* set reset to high */
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- udelay(10); /* wait 10us */
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- out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) & ~CFG_DUART_RST); /* set reset to low */
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- udelay(1000); /* wait 1ms */
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+ out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) | CFG_DUART_RST);
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+ udelay(10);
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+ out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) & ~CFG_DUART_RST);
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+ udelay(1000);
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/*
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* Set NAND-FLASH GPIO signals to default
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*/
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- out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) & ~(CFG_NAND_CLE | CFG_NAND_ALE));
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+ out_be32((void*)GPIO0_OR,
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+ in_be32((void*)GPIO0_OR) & ~(CFG_NAND_CLE | CFG_NAND_ALE));
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out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) | CFG_NAND_CE);
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/*
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@@ -210,7 +206,6 @@ int misc_init_r (void)
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return (0);
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}
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-
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/*
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* Check Board Identity:
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*/
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@@ -231,18 +226,6 @@ int checkboard (void)
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return 0;
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}
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-
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-phys_size_t initdram (int board_type)
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-{
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- unsigned long val;
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-
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- mtdcr(memcfga, mem_mb0cf);
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- val = mfdcr(memcfgd);
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-
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- return (4*1024*1024 << ((val & 0x000e0000) >> 17));
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-}
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-
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-
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#ifdef CONFIG_IDE_RESET
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void ide_set_reset(int on)
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{
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@@ -260,7 +243,6 @@ void ide_set_reset(int on)
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}
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#endif /* CONFIG_IDE_RESET */
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-
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void reset_phy(void)
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{
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#ifdef CONFIG_LXT971_NO_SLEEP
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@@ -272,7 +254,6 @@ void reset_phy(void)
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#endif
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}
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-
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#if defined(CFG_EEPROM_WREN)
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/* Input: <dev_addr> I2C address of EEPROM device to enable.
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* <state> -1: deliver current state
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@@ -290,17 +271,20 @@ int eeprom_write_enable (unsigned dev_addr, int state)
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switch (state) {
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case 1:
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/* Enable write access, clear bit GPIO0. */
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- out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) & ~CFG_EEPROM_WP);
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+ out_be32((void*)GPIO0_OR,
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+ in_be32((void*)GPIO0_OR) & ~CFG_EEPROM_WP);
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state = 0;
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break;
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case 0:
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/* Disable write access, set bit GPIO0. */
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- out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) | CFG_EEPROM_WP);
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+ out_be32((void*)GPIO0_OR,
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+ in_be32((void*)GPIO0_OR) | CFG_EEPROM_WP);
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state = 0;
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break;
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default:
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/* Read current status back. */
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- state = (0 == (in_be32((void*)GPIO0_OR) & CFG_EEPROM_WP));
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+ state = (0 == (in_be32((void*)GPIO0_OR) &
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+ CFG_EEPROM_WP));
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break;
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}
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}
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