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@@ -1,3 +1,65 @@
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+The 2 important dipswitches are configured as shown below:
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+
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+SW1 (for 33MHz SysClk)
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+----------------------
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+S1 S2 S3 S4 S5 S6 S7 S8
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+OFF OFF OFF OFF OFF OFF OFF ON
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+
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+SW7 (for Op-Code Flash and Boot Option H)
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+-----------------------------------------
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+S1 S2 S3 S4 S5 S6 S7 S8
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+OFF OFF OFF ON OFF OFF OFF OFF
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+
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+The EEPROM at location 0x52 is loaded with these 16 bytes:
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+C47042A6 05D7A190 40082350 0d050000
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+
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+SDR0_SDSTP0[ENG]: 1 : PLL's VCO is the source for PLL forward divisors
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+SDR0_SDSTP0[SRC]: 1 : Feedback originates from PLLOUTB
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+SDR0_SDSTP0[SEL]: 0 : Feedback selection is PLL output
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+SDR0_SDSTP0[TUNE]: 1000111000 : 10 <= M <= 22, 600MHz < VCO <= 900MHz
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+SDR0_SDSTP0[FBDV]: 4 : PLL feedback divisor
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+SDR0_SDSTP0[FBDVA]: 2 : PLL forward divisor A
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+SDR0_SDSTP0[FBDVB]: 5 : PLL forward divisor B
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+SDR0_SDSTP0[PRBDV0]: 1 : PLL primary divisor B
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+SDR0_SDSTP0[OPBDV0]: 2 : OPB clock divisor
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+SDR0_SDSTP0[LFBDV]: 1 : PLL local feedback divisor
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+SDR0_SDSTP0[PERDV0]: 3 : Peripheral clock divisor 0
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+SDR0_SDSTP0[MALDV0]: 2 : MAL clock divisor 0
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+SDR0_SDSTP0[PCIDV0]: 2 : Sync PCI clock divisor 0
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+SDR0_SDSTP0[PLLTIMER]: 7 : PLL locking timer
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+SDR0_SDSTP0[RW]: 1 : EBC ROM width: 16-bit
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+SDR0_SDSTP0[RL]: 0 : EBC ROM location: EBC
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+SDR0_SDSTP0[PAE]: 0 : PCI internal arbiter: disabled
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+SDR0_SDSTP0[PHCE]: 0 : PCI host configuration: disabled
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+SDR0_SDSTP0[ZM]: 3 : ZMII mode: RMII mode 100
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+SDR0_SDSTP0[CTE]: 0 : CPU trace: disabled
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+SDR0_SDSTP0[Nto1]: 0 : CPU/PLB ratio N/P: not N to 1
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+SDR0_SDSTP0[PAME]: 1 : PCI asynchronous mode: enabled
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+SDR0_SDSTP0[MEM]: 1 : Multiplex: EMAC
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+SDR0_SDSTP0[NE]: 0 : NDFC: disabled
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+SDR0_SDSTP0[NBW]: 0 : NDFC boot width: 8-bit
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+SDR0_SDSTP0[NBW]: 0 : NDFC boot page selection
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+SDR0_SDSTP0[NBAC]: 0 : NDFC boot address selection cycle: 3 Addr. Cycles, 1 Col. + 2 Row (512 page size)
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+SDR0_SDSTP0[NARE]: 0 : NDFC auto read : disabled
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+SDR0_SDSTP0[NRB]: 0 : NDFC Ready/Busy : Ready
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+SDR0_SDSTP0[NDRSC]: 33333 : NDFC device reset counter
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+SDR0_SDSTP0[NCG0]: 0 : NDFC/EBC chip select gating CS0 : EBC
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+SDR0_SDSTP0[NCG1]: 0 : NDFC/EBC chip select gating CS1 : EBC
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+SDR0_SDSTP0[NCG2]: 0 : NDFC/EBC chip select gating CS2 : EBC
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+SDR0_SDSTP0[NCG3]: 0 : NDFC/EBC chip select gating CS3 : EBC
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+SDR0_SDSTP0[NCRDC]: 3333 : NDFC device read count
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+
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+PPC440EP Clocking Configuration
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+
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+SysClk is 33.0MHz, M is 20, VCO is 660.0MHz, CPU is 330.0MHz, PLB is 132.0MHz
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+OPB is 66.0MHz, EBC is 44.0MHz, MAL is 66.0MHz, Sync PCI is 66.0MHz
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+
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+The above information is reported by Eugene O'Brien
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+<Eugene.O'Brien@advantechamt.com>. Thanks a lot.
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+
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+2007-08-06, Stefan Roese <sr@denx.de>
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+---------------------------------------------------------------------
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+
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The configuration for the AMCC 440EP eval board "Bamboo" was changed
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The configuration for the AMCC 440EP eval board "Bamboo" was changed
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to only use 384 kbytes of FLASH for the U-Boot image. This way the
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to only use 384 kbytes of FLASH for the U-Boot image. This way the
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redundant environment can be saved in the remaining 2 sectors of the
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redundant environment can be saved in the remaining 2 sectors of the
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Stefan Roese