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@@ -726,7 +726,9 @@ void mx28_power_set_vddio(uint32_t new_target, uint32_t new_brownout)
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clrsetbits_le32(&power_regs->hw_power_vddioctrl,
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POWER_VDDIOCTRL_TRG_MASK, diff);
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- if (powered_by_linreg)
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+ if (powered_by_linreg ||
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+ (readl(&power_regs->hw_power_sts) &
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+ POWER_STS_VDD5V_GT_VDDIO))
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early_delay(1500);
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else {
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while (!(readl(&power_regs->hw_power_sts) &
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@@ -761,7 +763,9 @@ void mx28_power_set_vddio(uint32_t new_target, uint32_t new_brownout)
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clrsetbits_le32(&power_regs->hw_power_vddioctrl,
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POWER_VDDIOCTRL_TRG_MASK, diff);
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- if (powered_by_linreg)
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+ if (powered_by_linreg ||
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+ (readl(&power_regs->hw_power_sts) &
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+ POWER_STS_VDD5V_GT_VDDIO))
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early_delay(1500);
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else {
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while (!(readl(&power_regs->hw_power_sts) &
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@@ -819,7 +823,9 @@ void mx28_power_set_vddd(uint32_t new_target, uint32_t new_brownout)
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clrsetbits_le32(&power_regs->hw_power_vdddctrl,
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POWER_VDDDCTRL_TRG_MASK, diff);
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- if (powered_by_linreg)
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+ if (powered_by_linreg ||
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+ (readl(&power_regs->hw_power_sts) &
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+ POWER_STS_VDD5V_GT_VDDIO))
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early_delay(1500);
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else {
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while (!(readl(&power_regs->hw_power_sts) &
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@@ -854,7 +860,9 @@ void mx28_power_set_vddd(uint32_t new_target, uint32_t new_brownout)
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clrsetbits_le32(&power_regs->hw_power_vdddctrl,
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POWER_VDDDCTRL_TRG_MASK, diff);
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- if (powered_by_linreg)
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+ if (powered_by_linreg ||
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+ (readl(&power_regs->hw_power_sts) &
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+ POWER_STS_VDD5V_GT_VDDIO))
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early_delay(1500);
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else {
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while (!(readl(&power_regs->hw_power_sts) &
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