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@@ -51,24 +51,36 @@
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* to be the base address for the chip, usually in the local
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* peripheral bus.
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*/
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-#if (CONFIG_SYS_SYSTEMACE_WIDTH == 8)
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+
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+static u32 base = CONFIG_SYS_SYSTEMACE_BASE;
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+static u32 width = CONFIG_SYS_SYSTEMACE_WIDTH;
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+
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+static void ace_writew(u16 val, unsigned off)
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+{
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+ if (width == 8) {
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#if !defined(__BIG_ENDIAN)
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-#define ace_readw(off) ((readb(CONFIG_SYS_SYSTEMACE_BASE+off)<<8) | \
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- (readb(CONFIG_SYS_SYSTEMACE_BASE+off+1)))
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-#define ace_writew(val, off) {writeb(val>>8, CONFIG_SYS_SYSTEMACE_BASE+off); \
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- writeb(val, CONFIG_SYS_SYSTEMACE_BASE+off+1);}
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+ writeb(val >> 8, base + off);
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+ writeb(val, base + off + 1);
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#else
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-#define ace_readw(off) ((readb(CONFIG_SYS_SYSTEMACE_BASE+off)) | \
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- (readb(CONFIG_SYS_SYSTEMACE_BASE+off+1)<<8))
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-#define ace_writew(val, off) {writeb(val, CONFIG_SYS_SYSTEMACE_BASE+off); \
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- writeb(val>>8, CONFIG_SYS_SYSTEMACE_BASE+off+1);}
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+ writeb(val, base + off);
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+ writeb(val >> 8, base + off + 1);
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#endif
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+ }
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+ out16(base + off, val);
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+}
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+
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+static u16 ace_readw(unsigned off)
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+{
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+ if (width == 8) {
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+#if !defined(__BIG_ENDIAN)
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+ return (readb(base + off) << 8) | readb(base + off + 1);
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#else
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-#define ace_readw(off) (in16(CONFIG_SYS_SYSTEMACE_BASE+off))
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-#define ace_writew(val, off) (out16(CONFIG_SYS_SYSTEMACE_BASE+off,val))
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+ return readb(base + off) | (readb(base + off + 1) << 8);
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#endif
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+ }
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-/* */
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+ return in16(base + off);
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+}
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static unsigned long systemace_read(int dev, unsigned long start,
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unsigned long blkcnt, void *buffer);
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@@ -121,7 +133,7 @@ block_dev_desc_t *systemace_get_dev(int dev)
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/*
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* Ensure the correct bus mode (8/16 bits) gets enabled
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*/
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- ace_writew(CONFIG_SYS_SYSTEMACE_WIDTH == 8 ? 0 : 0x0001, 0);
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+ ace_writew(width == 8 ? 0 : 0x0001, 0);
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init_part(&systemace_dev);
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