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@@ -36,7 +36,13 @@
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#define CONFIG_OMAP34XX 1 /* which is a 34XX */
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#define CONFIG_OMAP3_DEVKIT8000 1 /* working with DevKit8000 */
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-#define CONFIG_SYS_TEXT_BASE 0x80008000
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+/*
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+ * 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM
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+ * 64 bytes before this address should be set aside for u-boot.img's
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+ * header. That is 0x800FFFC0--0x80100000 should not be used for any
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+ * other needs.
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+ */
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+#define CONFIG_SYS_TEXT_BASE 0x80100000
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#define CONFIG_SDRC /* The chip has SDRC controller */
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@@ -347,7 +353,7 @@
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#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000
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#define CONFIG_SYS_NAND_U_BOOT_SIZE 0x200000
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-#define CONFIG_SYS_SPL_MALLOC_START 0x80108000
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+#define CONFIG_SYS_SPL_MALLOC_START 0x80208000
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#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 /* 1 MB */
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#endif /* __CONFIG_H */
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