Make Freescale local bus registers available for both 83xx and 85xx.

- Rename lbus83xx_t to fsl_lbus_t and move it to asm/fsl_lbc.h so that it
  can be shared by both 83xx and 85xx
- Remove lbus83xx_t and replace it with fsl_lbus_t in all 83xx boards
  files which use lbus83xx_t.
- Move FMR, FIR, FCR, FPAR, LTESR from mpc83xx.h to asm/fsl_lbc.h so that
  85xx can share them.

Signed-off-by: Jason Jin <Jason.Jin@freescale.com>
Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
Signed-off-by: Scott Wood <scottwood@freescale.com>

board/freescale/mpc8313erdb/sdram.c

@@ -110,7 +110,7 @@ static long fixed_sdram(void)
 phys_size_t initdram(int board_type)
 {
 	volatile immap_t *im = (volatile immap_t *)CONFIG_SYS_IMMR;
-	volatile lbus83xx_t *lbc = &im->lbus;
+	volatile fsl_lbus_t *lbc = &im->lbus;
 	u32 msize;
 
 	if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32)im)

board/freescale/mpc8349emds/mpc8349emds.c

@@ -192,7 +192,7 @@ int checkboard (void)
 void sdram_init(void)
 {
 	volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
-	volatile lbus83xx_t *lbc= &immap->lbus;
+	volatile fsl_lbus_t *lbc = &immap->lbus;
 	uint *sdram_addr = (uint *)CONFIG_SYS_LBC_SDRAM_BASE;
 
 	/*

board/freescale/mpc8349itx/mpc8349itx.c

@@ -221,7 +221,7 @@ int misc_init_f(void)
 		0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01
 	};
 	volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
-	volatile lbus83xx_t *lbus = &immap->lbus;
+	volatile fsl_lbus_t *lbus = &immap->lbus;
 
 	lbus->bank[3].br = CONFIG_SYS_BR3_PRELIM;
 	lbus->bank[3].or = CONFIG_SYS_OR3_PRELIM;

board/freescale/mpc8360emds/mpc8360emds.c

@@ -227,7 +227,7 @@ int checkboard(void)
 static int sdram_init(unsigned int base)
 {
 	volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
-	volatile lbus83xx_t *lbc = &immap->lbus;
+	volatile fsl_lbus_t *lbc = &immap->lbus;
 	const int sdram_size = CONFIG_SYS_LBC_SDRAM_SIZE * 1024 * 1024;
 	int rem = base % sdram_size;
 	uint *sdram_addr;

board/sbc8349/sbc8349.c

@@ -160,7 +160,7 @@ int checkboard (void)
 void sdram_init(void)
 {
 	volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
-	volatile lbus83xx_t *lbc= &immap->lbus;
+	volatile fsl_lbus_t *lbc = &immap->lbus;
 	uint *sdram_addr = (uint *)CONFIG_SYS_LBC_SDRAM_BASE;
 
 	puts("\n   SDRAM on Local Bus: ");

cpu/mpc83xx/cpu.c

@@ -148,7 +148,7 @@ int checkcpu(void)
 void upmconfig (uint upm, uint *table, uint size)
 {
 	volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
-	volatile lbus83xx_t *lbus = &immap->lbus;
+	volatile fsl_lbus_t *lbus = &immap->lbus;
 	volatile uchar *dummy = NULL;
 	const u32 msel = (upm + 4) << BR_MSEL_SHIFT;	/* What the MSEL field in BRn should be */
 	volatile u32 *mxmr = &lbus->mamr + upm;	/* Pointer to mamr, mbmr, or mcmr */

drivers/mtd/nand/fsl_elbc_nand.c

@@ -75,7 +75,7 @@ struct fsl_elbc_ctrl {
 	struct fsl_elbc_mtd *chips[MAX_BANKS];
 
 	/* device info */
-	lbus83xx_t *regs;
+	fsl_lbus_t *regs;
 	u8 __iomem *addr;        /* Address of assigned FCM buffer        */
 	unsigned int page;       /* Last page written to / read from      */
 	unsigned int read_bytes; /* Number of bytes read during command   */
@@ -171,7 +171,7 @@ static void set_addr(struct mtd_info *mtd, int column, int page_addr, int oob)
 	struct nand_chip *chip = mtd->priv;
 	struct fsl_elbc_mtd *priv = chip->priv;
 	struct fsl_elbc_ctrl *ctrl = priv->ctrl;
-	lbus83xx_t *lbc = ctrl->regs;
+	fsl_lbus_t *lbc = ctrl->regs;
 	int buf_num;
 
 	ctrl->page = page_addr;
@@ -211,7 +211,7 @@ static int fsl_elbc_run_command(struct mtd_info *mtd)
 	struct nand_chip *chip = mtd->priv;
 	struct fsl_elbc_mtd *priv = chip->priv;
 	struct fsl_elbc_ctrl *ctrl = priv->ctrl;
-	lbus83xx_t *lbc = ctrl->regs;
+	fsl_lbus_t *lbc = ctrl->regs;
 	long long end_tick;
 	u32 ltesr;
 
@@ -261,7 +261,7 @@ static void fsl_elbc_do_read(struct nand_chip *chip, int oob)
 {
 	struct fsl_elbc_mtd *priv = chip->priv;
 	struct fsl_elbc_ctrl *ctrl = priv->ctrl;
-	lbus83xx_t *lbc = ctrl->regs;
+	fsl_lbus_t *lbc = ctrl->regs;
 
 	if (priv->page_size) {
 		out_be32(&lbc->fir,
@@ -295,7 +295,7 @@ static void fsl_elbc_cmdfunc(struct mtd_info *mtd, unsigned int command,
 	struct nand_chip *chip = mtd->priv;
 	struct fsl_elbc_mtd *priv = chip->priv;
 	struct fsl_elbc_ctrl *ctrl = priv->ctrl;
-	lbus83xx_t *lbc = ctrl->regs;
+	fsl_lbus_t *lbc = ctrl->regs;
 
 	ctrl->use_mdr = 0;
 
@@ -633,7 +633,7 @@ static int fsl_elbc_wait(struct mtd_info *mtd, struct nand_chip *chip)
 {
 	struct fsl_elbc_mtd *priv = chip->priv;
 	struct fsl_elbc_ctrl *ctrl = priv->ctrl;
-	lbus83xx_t *lbc = ctrl->regs;
+	fsl_lbus_t *lbc = ctrl->regs;
 
 	if (ctrl->status != LTESR_CC)
 		return NAND_STATUS_FAIL;
@@ -693,13 +693,15 @@ static struct fsl_elbc_ctrl *elbc_ctrl;
 
 static void fsl_elbc_ctrl_init(void)
 {
-	immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
-
 	elbc_ctrl = kzalloc(sizeof(*elbc_ctrl), GFP_KERNEL);
 	if (!elbc_ctrl)
 		return;
 
-	elbc_ctrl->regs = &im->lbus;
+#ifdef CONFIG_MPC85xx
+	elbc_ctrl->regs = (void *)CONFIG_SYS_MPC85xx_LBC_ADDR;
+#else
+	elbc_ctrl->regs = &((immap_t *)CONFIG_SYS_IMMR)->lbus;
+#endif
 
 	/* clear event registers */
 	out_be32(&elbc_ctrl->regs->ltesr, LTESR_NAND_MASK);

include/asm-ppc/fsl_lbc.h

@@ -307,4 +307,134 @@
 #define LTEDR_RAWA	0x00400000 /* Read-after-write-atomic error checking disable	*/
 #define LTEDR_CSD	0x00080000 /* Chip select error checking disable		*/
 
+/* FMR - Flash Mode Register
+ */
+#define FMR_CWTO               0x0000F000
+#define FMR_CWTO_SHIFT         12
+#define FMR_BOOT               0x00000800
+#define FMR_ECCM               0x00000100
+#define FMR_AL                 0x00000030
+#define FMR_AL_SHIFT           4
+#define FMR_OP                 0x00000003
+#define FMR_OP_SHIFT           0
+
+/* FIR - Flash Instruction Register
+ */
+#define FIR_OP0                        0xF0000000
+#define FIR_OP0_SHIFT          28
+#define FIR_OP1                        0x0F000000
+#define FIR_OP1_SHIFT          24
+#define FIR_OP2                        0x00F00000
+#define FIR_OP2_SHIFT          20
+#define FIR_OP3                        0x000F0000
+#define FIR_OP3_SHIFT          16
+#define FIR_OP4                        0x0000F000
+#define FIR_OP4_SHIFT          12
+#define FIR_OP5                        0x00000F00
+#define FIR_OP5_SHIFT          8
+#define FIR_OP6                        0x000000F0
+#define FIR_OP6_SHIFT          4
+#define FIR_OP7                        0x0000000F
+#define FIR_OP7_SHIFT          0
+#define FIR_OP_NOP             0x0 /* No operation and end of sequence */
+#define FIR_OP_CA              0x1 /* Issue current column address */
+#define FIR_OP_PA              0x2 /* Issue current block+page address */
+#define FIR_OP_UA              0x3 /* Issue user defined address */
+#define FIR_OP_CM0             0x4 /* Issue command from FCR[CMD0] */
+#define FIR_OP_CM1             0x5 /* Issue command from FCR[CMD1] */
+#define FIR_OP_CM2             0x6 /* Issue command from FCR[CMD2] */
+#define FIR_OP_CM3             0x7 /* Issue command from FCR[CMD3] */
+#define FIR_OP_WB              0x8 /* Write FBCR bytes from FCM buffer */
+#define FIR_OP_WS              0x9 /* Write 1 or 2 bytes from MDR[AS] */
+#define FIR_OP_RB              0xA /* Read FBCR bytes to FCM buffer */
+#define FIR_OP_RS              0xB /* Read 1 or 2 bytes to MDR[AS] */
+#define FIR_OP_CW0             0xC /* Wait then issue FCR[CMD0] */
+#define FIR_OP_CW1             0xD /* Wait then issue FCR[CMD1] */
+#define FIR_OP_RBW             0xE /* Wait then read FBCR bytes */
+#define FIR_OP_RSW             0xF /* Wait then read 1 or 2 bytes */
+
+/* FCR - Flash Command Register
+ */
+#define FCR_CMD0               0xFF000000
+#define FCR_CMD0_SHIFT         24
+#define FCR_CMD1               0x00FF0000
+#define FCR_CMD1_SHIFT         16
+#define FCR_CMD2               0x0000FF00
+#define FCR_CMD2_SHIFT         8
+#define FCR_CMD3               0x000000FF
+#define FCR_CMD3_SHIFT         0
+/* FBAR - Flash Block Address Register
+ */
+#define FBAR_BLK               0x00FFFFFF
+
+/* FPAR - Flash Page Address Register
+ */
+#define FPAR_SP_PI             0x00007C00
+#define FPAR_SP_PI_SHIFT       10
+#define FPAR_SP_MS             0x00000200
+#define FPAR_SP_CI             0x000001FF
+#define FPAR_SP_CI_SHIFT       0
+#define FPAR_LP_PI             0x0003F000
+#define FPAR_LP_PI_SHIFT       12
+#define FPAR_LP_MS             0x00000800
+#define FPAR_LP_CI             0x000007FF
+#define FPAR_LP_CI_SHIFT       0
+
+/* LTESR - Transfer Error Status Register
+ */
+#define LTESR_BM               0x80000000
+#define LTESR_FCT              0x40000000
+#define LTESR_PAR              0x20000000
+#define LTESR_WP               0x04000000
+#define LTESR_ATMW             0x00800000
+#define LTESR_ATMR             0x00400000
+#define LTESR_CS               0x00080000
+#define LTESR_CC               0x00000001
+
+#ifndef __ASSEMBLY__
+/*
+ * Local Bus Controller Registers.
+ */
+typedef struct lbus_bank {
+	u32 br;                 /* Base Register */
+	u32 or;                 /* Option Register */
+} lbus_bank_t;
+
+typedef struct fsl_lbus {
+	lbus_bank_t bank[8];
+	u8 res0[0x28];
+	u32 mar;                /* UPM Address Register */
+	u8 res1[0x4];
+	u32 mamr;               /* UPMA Mode Register */
+	u32 mbmr;               /* UPMB Mode Register */
+	u32 mcmr;               /* UPMC Mode Register */
+	u8 res2[0x8];
+	u32 mrtpr;              /* Memory Refresh Timer Prescaler Register */
+	u32 mdr;                /* UPM Data Register */
+	u8 res3[0x4];
+	u32 lsor;               /* Special Operation Initiation Register */
+	u32 lsdmr;              /* SDRAM Mode Register */
+	u8 res4[0x8];
+	u32 lurt;               /* UPM Refresh Timer */
+	u32 lsrt;               /* SDRAM Refresh Timer */
+	u8 res5[0x8];
+	u32 ltesr;              /* Transfer Error Status Register */
+	u32 ltedr;              /* Transfer Error Disable Register */
+	u32 lteir;              /* Transfer Error Interrupt Register */
+	u32 lteatr;             /* Transfer Error Attributes Register */
+	u32 ltear;               /* Transfer Error Address Register */
+	u8 res6[0xC];
+	u32 lbcr;               /* Configuration Register */
+	u32 lcrr;               /* Clock Ratio Register */
+	u8 res7[0x8];
+	u32 fmr;                /* Flash Mode Register */
+	u32 fir;                /* Flash Instruction Register */
+	u32 fcr;                /* Flash Command Register */
+	u32 fbar;               /* Flash Block Addr Register */
+	u32 fpar;               /* Flash Page Addr Register */
+	u32 fbcr;               /* Flash Byte Count Register */
+	u8 res8[0xF08];
+} fsl_lbus_t;
+#endif /* __ASSEMBLY__ */
+
 #endif /* __ASM_PPC_FSL_LBC_H */

include/asm-ppc/immap_83xx.h

@@ -31,6 +31,7 @@
 #include <asm/types.h>
 #include <asm/fsl_i2c.h>
 #include <asm/mpc8xxx_spi.h>
+#include <asm/fsl_lbc.h>
 
 /*
  * Local Access Window
@@ -342,50 +343,6 @@ typedef struct duart83xx {
 	u8 res2[0xEC];
 } duart83xx_t;
 
-/*
- * Local Bus Controller Registers
- */
-typedef struct lbus_bank {
-	u32 br;			/* Base Register */
-	u32 or;			/* Option Register */
-} lbus_bank_t;
-
-typedef struct lbus83xx {
-	lbus_bank_t bank[8];
-	u8 res0[0x28];
-	u32 mar;		/* UPM Address Register */
-	u8 res1[0x4];
-	u32 mamr;		/* UPMA Mode Register */
-	u32 mbmr;		/* UPMB Mode Register */
-	u32 mcmr;		/* UPMC Mode Register */
-	u8 res2[0x8];
-	u32 mrtpr;		/* Memory Refresh Timer Prescaler Register */
-	u32 mdr;		/* UPM Data Register */
-	u8 res3[0x4];
-	u32 lsor;		/* Special Operation Initiation Register */
-	u32 lsdmr;		/* SDRAM Mode Register */
-	u8 res4[0x8];
-	u32 lurt;		/* UPM Refresh Timer */
-	u32 lsrt;		/* SDRAM Refresh Timer */
-	u8 res5[0x8];
-	u32 ltesr;		/* Transfer Error Status Register */
-	u32 ltedr;		/* Transfer Error Disable Register */
-	u32 lteir;		/* Transfer Error Interrupt Register */
-	u32 lteatr;		/* Transfer Error Attributes Register */
-	u32 ltear;		/* Transfer Error Address Register */
-	u8 res6[0xC];
-	u32 lbcr;		/* Configuration Register */
-	u32 lcrr;		/* Clock Ratio Register */
-	u8 res7[0x8];
-	u32 fmr;		/* Flash Mode Register */
-	u32 fir;		/* Flash Instruction Register */
-	u32 fcr;		/* Flash Command Register */
-	u32 fbar;		/* Flash Block Addr Register */
-	u32 fpar;		/* Flash Page Addr Register */
-	u32 fbcr;		/* Flash Byte Count Register */
-	u8 res8[0xF08];
-} lbus83xx_t;
-
 /*
  * DMA/Messaging Unit
  */
@@ -614,7 +571,7 @@ typedef struct immap {
 	u8			res2[0x1300];
 	duart83xx_t		duart[2];	/* DUART */
 	u8			res3[0x900];
-	lbus83xx_t		lbus;		/* Local Bus Controller Registers */
+	fsl_lbus_t		lbus;	/* Local Bus Controller Registers */
 	u8			res4[0x1000];
 	spi8xxx_t		spi;		/* Serial Peripheral Interface */
 	dma83xx_t		dma;		/* DMA */
@@ -648,7 +605,7 @@ typedef struct immap {
 	u8			res1[0x1300];
 	duart83xx_t		duart[2];	/* DUART */
 	u8			res2[0x900];
-	lbus83xx_t		lbus;		/* Local Bus Controller Registers */
+	fsl_lbus_t		lbus;	/* Local Bus Controller Registers */
 	u8			res3[0x1000];
 	spi8xxx_t		spi;		/* Serial Peripheral Interface */
 	dma83xx_t		dma;		/* DMA */
@@ -683,7 +640,7 @@ typedef struct immap {
 	u8			res1[0x1300];
 	duart83xx_t		duart[2];	/* DUART */
 	u8			res2[0x900];
-	lbus83xx_t		lbus;		/* Local Bus Controller Registers */
+	fsl_lbus_t		lbus;	/* Local Bus Controller Registers */
 	u8			res3[0x1000];
 	spi8xxx_t		spi;		/* Serial Peripheral Interface */
 	dma83xx_t		dma;		/* DMA */
@@ -728,7 +685,7 @@ typedef struct immap {
 	u8			res1[0x1300];
 	duart83xx_t		duart[2];	/* DUART */
 	u8			res2[0x900];
-	lbus83xx_t		lbus;		/* Local Bus Controller Registers */
+	fsl_lbus_t		lbus;	/* Local Bus Controller Registers */
 	u8			res3[0x1000];
 	spi8xxx_t		spi;		/* Serial Peripheral Interface */
 	dma83xx_t		dma;		/* DMA */
@@ -778,7 +735,7 @@ typedef struct immap {
 	u8			res4[0x1300];
 	duart83xx_t		duart[2];	/* DUART */
 	u8			res5[0x900];
-	lbus83xx_t		lbus;		/* Local Bus Controller Registers */
+	fsl_lbus_t		lbus;	/* Local Bus Controller Registers */
 	u8			res6[0x2000];
 	dma83xx_t		dma;		/* DMA */
 	pciconf83xx_t		pci_conf[1];	/* PCI Software Configuration Registers */
@@ -817,7 +774,7 @@ typedef struct immap {
 	u8			res3[0x1300];
 	duart83xx_t		duart[2];	/* DUART */
 	u8			res4[0x900];
-	lbus83xx_t		lbus;		/* Local Bus Controller Registers */
+	fsl_lbus_t		lbus;	/* Local Bus Controller Registers */
 	u8			res5[0x2000];
 	dma83xx_t		dma;		/* DMA */
 	pciconf83xx_t		pci_conf[1];	/* PCI Software Configuration Registers */

include/asm-ppc/immap_85xx.h

@@ -13,6 +13,7 @@
 
 #include <asm/types.h>
 #include <asm/fsl_i2c.h>
+#include <asm/fsl_lbc.h>
 
 /*
  * Local-Access Registers and ECM Registers(0x0000-0x2000)

include/mpc83xx.h

@@ -1147,91 +1147,6 @@
  */
 #define PMCCR1_POWER_OFF		0x00000020
 
-/* FMR - Flash Mode Register
- */
-#define FMR_CWTO		0x0000F000
-#define FMR_CWTO_SHIFT		12
-#define FMR_BOOT		0x00000800
-#define FMR_ECCM		0x00000100
-#define FMR_AL			0x00000030
-#define FMR_AL_SHIFT		4
-#define FMR_OP			0x00000003
-#define FMR_OP_SHIFT		0
-
-/* FIR - Flash Instruction Register
- */
-#define FIR_OP0			0xF0000000
-#define FIR_OP0_SHIFT		28
-#define FIR_OP1			0x0F000000
-#define FIR_OP1_SHIFT		24
-#define FIR_OP2			0x00F00000
-#define FIR_OP2_SHIFT		20
-#define FIR_OP3			0x000F0000
-#define FIR_OP3_SHIFT		16
-#define FIR_OP4			0x0000F000
-#define FIR_OP4_SHIFT		12
-#define FIR_OP5			0x00000F00
-#define FIR_OP5_SHIFT		8
-#define FIR_OP6			0x000000F0
-#define FIR_OP6_SHIFT		4
-#define FIR_OP7			0x0000000F
-#define FIR_OP7_SHIFT		0
-#define FIR_OP_NOP		0x0 /* No operation and end of sequence */
-#define FIR_OP_CA		0x1 /* Issue current column address */
-#define FIR_OP_PA		0x2 /* Issue current block+page address */
-#define FIR_OP_UA		0x3 /* Issue user defined address */
-#define FIR_OP_CM0		0x4 /* Issue command from FCR[CMD0] */
-#define FIR_OP_CM1		0x5 /* Issue command from FCR[CMD1] */
-#define FIR_OP_CM2		0x6 /* Issue command from FCR[CMD2] */
-#define FIR_OP_CM3		0x7 /* Issue command from FCR[CMD3] */
-#define FIR_OP_WB		0x8 /* Write FBCR bytes from FCM buffer */
-#define FIR_OP_WS		0x9 /* Write 1 or 2 bytes from MDR[AS] */
-#define FIR_OP_RB		0xA /* Read FBCR bytes to FCM buffer */
-#define FIR_OP_RS		0xB /* Read 1 or 2 bytes to MDR[AS] */
-#define FIR_OP_CW0		0xC /* Wait then issue FCR[CMD0] */
-#define FIR_OP_CW1		0xD /* Wait then issue FCR[CMD1] */
-#define FIR_OP_RBW		0xE /* Wait then read FBCR bytes */
-#define FIR_OP_RSW		0xF /* Wait then read 1 or 2 bytes */
-
-/* FCR - Flash Command Register
- */
-#define FCR_CMD0		0xFF000000
-#define FCR_CMD0_SHIFT		24
-#define FCR_CMD1		0x00FF0000
-#define FCR_CMD1_SHIFT		16
-#define FCR_CMD2		0x0000FF00
-#define FCR_CMD2_SHIFT		8
-#define FCR_CMD3		0x000000FF
-#define FCR_CMD3_SHIFT		0
-
-/* FBAR - Flash Block Address Register
- */
-#define FBAR_BLK		0x00FFFFFF
-
-/* FPAR - Flash Page Address Register
- */
-#define FPAR_SP_PI		0x00007C00
-#define FPAR_SP_PI_SHIFT	10
-#define FPAR_SP_MS		0x00000200
-#define FPAR_SP_CI		0x000001FF
-#define FPAR_SP_CI_SHIFT	0
-#define FPAR_LP_PI		0x0003F000
-#define FPAR_LP_PI_SHIFT	12
-#define FPAR_LP_MS		0x00000800
-#define FPAR_LP_CI		0x000007FF
-#define FPAR_LP_CI_SHIFT	0
-
-/* LTESR - Transfer Error Status Register
- */
-#define LTESR_BM		0x80000000
-#define LTESR_FCT		0x40000000
-#define LTESR_PAR		0x20000000
-#define LTESR_WP		0x04000000
-#define LTESR_ATMW		0x00800000
-#define LTESR_ATMR		0x00400000
-#define LTESR_CS		0x00080000
-#define LTESR_CC		0x00000001
-
 /* DDRCDR - DDR Control Driver Register
  */
 #define DDRCDR_DHC_EN		0x80000000

nand_spl/nand_boot_fsl_elbc.c

@@ -33,7 +33,7 @@
 
 static void nand_wait(void)
 {
-	lbus83xx_t *regs = (lbus83xx_t *)(CONFIG_SYS_IMMR + 0x5000);
+	fsl_lbus_t *regs = (fsl_lbus_t *)(CONFIG_SYS_IMMR + 0x5000);
 
 	for (;;) {
 		uint32_t status = in_be32(&regs->ltesr);
@@ -50,7 +50,7 @@ static void nand_wait(void)
 
 static void nand_load(unsigned int offs, int uboot_size, uchar *dst)
 {
-	lbus83xx_t *regs = (lbus83xx_t *)(CONFIG_SYS_IMMR + 0x5000);
+	fsl_lbus_t *regs = (fsl_lbus_t *)(CONFIG_SYS_IMMR + 0x5000);
 	uchar *buf = (uchar *)CONFIG_SYS_NAND_BASE;
 	int large = in_be32(&regs->bank[0].or) & OR_FCM_PGS;
 	int block_shift = large ? 17 : 14;