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@@ -20,6 +20,7 @@
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#include <common.h>
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#include <common.h>
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#include <malloc.h>
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#include <malloc.h>
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#include <spi.h>
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#include <spi.h>
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+#include <fdtdec.h>
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#include <asm/arch/clk.h>
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#include <asm/arch/clk.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/cpu.h>
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#include <asm/arch/cpu.h>
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@@ -28,16 +29,20 @@
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#include <asm/arch-exynos/spi.h>
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#include <asm/arch-exynos/spi.h>
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#include <asm/io.h>
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#include <asm/io.h>
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+DECLARE_GLOBAL_DATA_PTR;
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+
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/* Information about each SPI controller */
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/* Information about each SPI controller */
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struct spi_bus {
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struct spi_bus {
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enum periph_id periph_id;
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enum periph_id periph_id;
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s32 frequency; /* Default clock frequency, -1 for none */
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s32 frequency; /* Default clock frequency, -1 for none */
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struct exynos_spi *regs;
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struct exynos_spi *regs;
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int inited; /* 1 if this bus is ready for use */
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int inited; /* 1 if this bus is ready for use */
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+ int node;
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};
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};
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/* A list of spi buses that we know about */
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/* A list of spi buses that we know about */
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static struct spi_bus spi_bus[EXYNOS5_SPI_NUM_CONTROLLERS];
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static struct spi_bus spi_bus[EXYNOS5_SPI_NUM_CONTROLLERS];
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+static unsigned int bus_count;
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struct exynos_spi_slave {
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struct exynos_spi_slave {
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struct spi_slave slave;
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struct spi_slave slave;
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@@ -50,7 +55,7 @@ struct exynos_spi_slave {
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static struct spi_bus *spi_get_bus(unsigned dev_index)
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static struct spi_bus *spi_get_bus(unsigned dev_index)
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{
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{
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- if (dev_index < EXYNOS5_SPI_NUM_CONTROLLERS)
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+ if (dev_index < bus_count)
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return &spi_bus[dev_index];
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return &spi_bus[dev_index];
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debug("%s: invalid bus %d", __func__, dev_index);
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debug("%s: invalid bus %d", __func__, dev_index);
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@@ -347,21 +352,100 @@ static inline struct exynos_spi *get_spi_base(int dev_index)
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(dev_index - 3);
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(dev_index - 3);
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}
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}
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+/*
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+ * Read the SPI config from the device tree node.
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+ *
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+ * @param blob FDT blob to read from
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+ * @param node Node offset to read from
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+ * @param bus SPI bus structure to fill with information
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+ * @return 0 if ok, or -FDT_ERR_NOTFOUND if something was missing
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+ */
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+static int spi_get_config(const void *blob, int node, struct spi_bus *bus)
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+{
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+ bus->node = node;
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+ bus->regs = (struct exynos_spi *)fdtdec_get_addr(blob, node, "reg");
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+ bus->periph_id = pinmux_decode_periph_id(blob, node);
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+
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+ if (bus->periph_id == PERIPH_ID_NONE) {
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+ debug("%s: Invalid peripheral ID %d\n", __func__,
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+ bus->periph_id);
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+ return -FDT_ERR_NOTFOUND;
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+ }
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+
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+ /* Use 500KHz as a suitable default */
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+ bus->frequency = fdtdec_get_int(blob, node, "spi-max-frequency",
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+ 500000);
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+
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+ return 0;
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+}
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+
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+/*
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+ * Process a list of nodes, adding them to our list of SPI ports.
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+ *
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+ * @param blob fdt blob
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+ * @param node_list list of nodes to process (any <=0 are ignored)
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+ * @param count number of nodes to process
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+ * @param is_dvc 1 if these are DVC ports, 0 if standard I2C
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+ * @return 0 if ok, -1 on error
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+ */
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+static int process_nodes(const void *blob, int node_list[], int count)
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+{
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+ int i;
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+
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+ /* build the i2c_controllers[] for each controller */
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+ for (i = 0; i < count; i++) {
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+ int node = node_list[i];
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+ struct spi_bus *bus;
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+
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+ if (node <= 0)
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+ continue;
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+
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+ bus = &spi_bus[i];
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+ if (spi_get_config(blob, node, bus)) {
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+ printf("exynos spi_init: failed to decode bus %d\n",
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+ i);
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+ return -1;
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+ }
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+
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+ debug("spi: controller bus %d at %p, periph_id %d\n",
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+ i, bus->regs, bus->periph_id);
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+ bus->inited = 1;
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+ bus_count++;
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+ }
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+
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+ return 0;
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+}
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+
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/* Sadly there is no error return from this function */
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/* Sadly there is no error return from this function */
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void spi_init(void)
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void spi_init(void)
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{
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{
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- int i;
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+ int count;
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+
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+#ifdef CONFIG_OF_CONTROL
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+ int node_list[EXYNOS5_SPI_NUM_CONTROLLERS];
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+ const void *blob = gd->fdt_blob;
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+
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+ count = fdtdec_find_aliases_for_id(blob, "spi",
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+ COMPAT_SAMSUNG_EXYNOS_SPI, node_list,
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+ EXYNOS5_SPI_NUM_CONTROLLERS);
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+ if (process_nodes(blob, node_list, count))
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+ return;
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+
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+#else
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struct spi_bus *bus;
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struct spi_bus *bus;
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- for (i = 0; i < EXYNOS5_SPI_NUM_CONTROLLERS; i++) {
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- bus = &spi_bus[i];
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- bus->regs = get_spi_base(i);
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- bus->periph_id = PERIPH_ID_SPI0 + i;
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+ for (count = 0; count < EXYNOS5_SPI_NUM_CONTROLLERS; count++) {
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+ bus = &spi_bus[count];
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+ bus->regs = get_spi_base(count);
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+ bus->periph_id = PERIPH_ID_SPI0 + count;
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/* Although Exynos5 supports upto 50Mhz speed,
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/* Although Exynos5 supports upto 50Mhz speed,
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* we are setting it to 10Mhz for safe side
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* we are setting it to 10Mhz for safe side
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*/
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*/
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bus->frequency = 10000000;
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bus->frequency = 10000000;
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bus->inited = 1;
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bus->inited = 1;
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+ bus->node = 0;
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+ bus_count = EXYNOS5_SPI_NUM_CONTROLLERS;
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}
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}
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+#endif
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}
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}
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