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@@ -1920,6 +1920,52 @@ typedef struct ccsr_gur {
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u32 gpindr; /* General-purpose input data */
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u8 res5[12];
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u32 pmuxcr; /* Alt. function signal multiplex control */
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+#if defined(CONFIG_P1010) || defined(CONFIG_P1014)
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+#define MPC85xx_PMUXCR_TSEC1_0_1588 0x40000000
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+#define MPC85xx_PMUXCR_TSEC1_0_RES 0xC0000000
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+#define MPC85xx_PMUXCR_TSEC1_1_1588_TRIG 0x10000000
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+#define MPC85xx_PMUXCR_TSEC1_1_GPIO_12 0x20000000
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+#define MPC85xx_PMUXCR_TSEC1_1_RES 0x30000000
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+#define MPC85xx_PMUXCR_TSEC1_2_DMA 0x04000000
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+#define MPC85xx_PMUXCR_TSEC1_2_GPIO 0x08000000
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+#define MPC85xx_PMUXCR_TSEC1_2_RES 0x0C000000
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+#define MPC85xx_PMUXCR_TSEC1_3_RES 0x01000000
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+#define MPC85xx_PMUXCR_TSEC1_3_GPIO_15 0x02000000
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+#define MPC85xx_PMUXCR_IFC_ADDR16_SDHC 0x00400000
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+#define MPC85xx_PMUXCR_IFC_ADDR16_USB 0x00800000
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+#define MPC85xx_PMUXCR_IFC_ADDR16_IFC_CS2 0x00C00000
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+#define MPC85xx_PMUXCR_IFC_ADDR17_18_SDHC 0x00100000
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+#define MPC85xx_PMUXCR_IFC_ADDR17_18_USB 0x00200000
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+#define MPC85xx_PMUXCR_IFC_ADDR17_18_DMA 0x00300000
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+#define MPC85xx_PMUXCR_IFC_ADDR19_SDHC_DATA 0x00040000
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+#define MPC85xx_PMUXCR_IFC_ADDR19_USB 0x00080000
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+#define MPC85xx_PMUXCR_IFC_ADDR19_DMA 0x000C0000
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+#define MPC85xx_PMUXCR_IFC_ADDR20_21_SDHC_DATA 0x00010000
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+#define MPC85xx_PMUXCR_IFC_ADDR20_21_USB 0x00020000
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+#define MPC85xx_PMUXCR_IFC_ADDR20_21_RES 0x00030000
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+#define MPC85xx_PMUXCR_IFC_ADDR22_SDHC 0x00004000
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+#define MPC85xx_PMUXCR_IFC_ADDR22_USB 0x00008000
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+#define MPC85xx_PMUXCR_IFC_ADDR22_RES 0x0000C000
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+#define MPC85xx_PMUXCR_IFC_ADDR23_SDHC 0x00001000
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+#define MPC85xx_PMUXCR_IFC_ADDR23_USB 0x00002000
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+#define MPC85xx_PMUXCR_IFC_ADDR23_RES 0x00003000
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+#define MPC85xx_PMUXCR_IFC_ADDR24_SDHC 0x00000400
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+#define MPC85xx_PMUXCR_IFC_ADDR24_USB 0x00000800
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+#define MPC85xx_PMUXCR_IFC_ADDR24_RES 0x00000C00
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+#define MPC85xx_PMUXCR_IFC_PAR_PERR_RES 0x00000300
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+#define MPC85xx_PMUXCR_IFC_PAR_PERR_USB 0x00000200
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+#define MPC85xx_PMUXCR_LCLK_RES 0x00000040
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+#define MPC85xx_PMUXCR_LCLK_USB 0x00000080
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+#define MPC85xx_PMUXCR_LCLK_IFC_CS3 0x000000C0
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+#define MPC85xx_PMUXCR_SPI_RES 0x00000030
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+#define MPC85xx_PMUXCR_SPI_GPIO 0x00000020
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+#define MPC85xx_PMUXCR_CAN1_UART 0x00000004
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+#define MPC85xx_PMUXCR_CAN1_TDM 0x00000008
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+#define MPC85xx_PMUXCR_CAN1_RES 0x0000000C
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+#define MPC85xx_PMUXCR_CAN2_UART 0x00000001
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+#define MPC85xx_PMUXCR_CAN2_TDM 0x00000002
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+#define MPC85xx_PMUXCR_CAN2_RES 0x00000003
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+#endif
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#define MPC85xx_PMUXCR_SD_DATA 0x80000000
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#define MPC85xx_PMUXCR_SDHC_CD 0x40000000
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#define MPC85xx_PMUXCR_SDHC_WP 0x20000000
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@@ -1944,6 +1990,31 @@ typedef struct ccsr_gur {
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#define MPC85xx_PMUXCR_SPI 0x00000000
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#endif
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u32 pmuxcr2; /* Alt. function signal multiplex control 2 */
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+#if defined(CONFIG_P1010) || defined(CONFIG_P1014)
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+#define MPC85xx_PMUXCR2_UART_GPIO 0x40000000
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+#define MPC85xx_PMUXCR2_UART_TDM 0x80000000
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+#define MPC85xx_PMUXCR2_UART_RES 0xC0000000
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+#define MPC85xx_PMUXCR2_IRQ2_TRIG_IN 0x10000000
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+#define MPC85xx_PMUXCR2_IRQ2_RES 0x30000000
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+#define MPC85xx_PMUXCR2_IRQ3_SRESET 0x04000000
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+#define MPC85xx_PMUXCR2_IRQ3_RES 0x0C000000
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+#define MPC85xx_PMUXCR2_GPIO01_DRVVBUS 0x01000000
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+#define MPC85xx_PMUXCR2_GPIO01_RES 0x03000000
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+#define MPC85xx_PMUXCR2_GPIO23_CKSTP 0x00400000
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+#define MPC85xx_PMUXCR2_GPIO23_RES 0x00800000
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+#define MPC85xx_PMUXCR2_GPIO23_USB 0x00C00000
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+#define MPC85xx_PMUXCR2_GPIO4_MCP 0x00100000
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+#define MPC85xx_PMUXCR2_GPIO4_RES 0x00200000
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+#define MPC85xx_PMUXCR2_GPIO4_CLK_OUT 0x00300000
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+#define MPC85xx_PMUXCR2_GPIO5_UDE 0x00040000
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+#define MPC85xx_PMUXCR2_GPIO5_RES 0x00080000
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+#define MPC85xx_PMUXCR2_READY_ASLEEP 0x00020000
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+#define MPC85xx_PMUXCR2_DDR_ECC_MUX 0x00010000
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+#define MPC85xx_PMUXCR2_DEBUG_PORT_EXPOSE 0x00008000
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+#define MPC85xx_PMUXCR2_POST_EXPOSE 0x00004000
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+#define MPC85xx_PMUXCR2_DEBUG_MUX_SEL_USBPHY 0x00002000
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+#define MPC85xx_PMUXCR2_PLL_LKDT_EXPOSE 0x00001000
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+#endif
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#if defined(CONFIG_P1013) || defined(CONFIG_P1022)
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#define MPC85xx_PMUXCR2_ETSECUSB_MASK 0x001f1000
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#define MPC85xx_PMUXCR2_USB 0x00150000
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