* Patch by Pierre Aubert, 11 Mar 2004:

  - add bitmap command and splash screen support in cfb console
  - add [optional] origin in the bitmap display command

* Patch by Travis Sawyer, 11 Mar 2004:
  Fix ocotea board early init interrupt setup.

* Patch by Thomas Viehweger, 11 Mar 2004:
  Remove redundand code; add  PCI-specific bits to include/mpc8260.h

CHANGELOG

@@ -2,6 +2,16 @@
 Changes for U-Boot 1.0.2:
 ======================================================================
 
+* Patch by  Pierre Aubert, 11 Mar 2004:
+  - add bitmap command and splash screen support in cfb console
+  - add [optional] origin in the bitmap display command
+
+* Patch by Travis Sawyer, 11 Mar 2004:
+  Fix ocotea board early init interrupt setup.
+
+* Patch by Thomas Viehweger, 11 Mar 2004:
+  Remove redundand code; add  PCI-specific bits to include/mpc8260.h
+
 * Patch by Stephan Linz, 09 Mar 2004
   - Add support for the SSV ADNP/ESC1 (Nios Softcore)
 

board/ocotea/ocotea.c

@@ -36,6 +36,7 @@ void fpga_init (void);
 
 int board_early_init_f (void)
 {
+	unsigned long mfr;
 	/*-------------------------------------------------------------------------+
 	  | Initialize EBC CONFIG
 	  +-------------------------------------------------------------------------*/
@@ -116,6 +117,23 @@ int board_early_init_f (void)
 	mtdcr (uic1vr, 0x00000001);	/* int31 highest, base=0x000 */
 	mtdcr (uic1sr, 0xffffffff);	/* clear all */
 
+	mtdcr (uic2sr, 0xffffffff);	/* clear all */
+	mtdcr (uic2er, 0x00000000);	/* disable all */
+	mtdcr (uic2cr, 0x00000000);	/* all non-critical */
+	mtdcr (uic2pr, 0xffffffff);	/* per ref-board manual */
+	mtdcr (uic2tr, 0x00ff8c0f);	/* per ref-board manual */
+	mtdcr (uic2vr, 0x00000001);	/* int31 highest, base=0x000 */
+	mtdcr (uic2sr, 0xffffffff);	/* clear all */
+
+	mtdcr (uicb0sr, 0xfc000000); /* clear all */
+	mtdcr (uicb0er, 0x00000000); /* disable all */
+	mtdcr (uicb0cr, 0x00000000); /* all non-critical */
+	mtdcr (uicb0pr, 0xfc000000); /* */
+	mtdcr (uicb0tr, 0x00000000); /* */
+	mtdcr (uicb0vr, 0x00000001); /* */
+	mfsdr (sdr_mfr, mfr);
+	mfr &= ~SDR0_MFR_ECS_MASK;
+/*	mtsdr(sdr_mfr, mfr); */
 	fpga_init();
 
 	return 0;

common/cmd_bmp.c

@@ -32,7 +32,7 @@
 #if (CONFIG_COMMANDS & CFG_CMD_BMP)
 
 static int bmp_info (ulong addr);
-static int bmp_display (ulong addr);
+static int bmp_display (ulong addr, int x, int y);
 
 /*
  * Subroutine:  do_bmp
@@ -47,6 +47,7 @@ static int bmp_display (ulong addr);
 int do_bmp(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 {
 	ulong addr;
+	int x = 0, y = 0;
 
 	switch (argc) {
 	case 2:		/* use load_addr as default address */
@@ -55,6 +56,11 @@ int do_bmp(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 	case 3:		/* use argument */
 		addr = simple_strtoul(argv[2], NULL, 16);
 		break;
+	case 5:
+		addr = simple_strtoul(argv[2], NULL, 16);
+	        x = simple_strtoul(argv[3], NULL, 10);
+	        y = simple_strtoul(argv[4], NULL, 10);
+	        break;
 	default:
 		printf ("Usage:\n%s\n", cmdtp->usage);
 		return 1;
@@ -66,7 +72,7 @@ int do_bmp(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 	if (strncmp(argv[1],"info",1) == 0) {
 		return (bmp_info(addr));
 	} else if (strncmp(argv[1],"display",1) == 0) {
-		return (bmp_display(addr));
+	    return (bmp_display(addr, x, y));
 	} else {
 		printf ("Usage:\n%s\n", cmdtp->usage);
 		return 1;
@@ -74,10 +80,10 @@ int do_bmp(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 }
 
 U_BOOT_CMD(
-	bmp,	3,	1,	do_bmp,
+	bmp,	5,	1,	do_bmp,
 	"bmp     - manipulate BMP image data\n",
-	"info <imageAddr>    - display image info\n"
-	"bmp display <imageAddr> - display image\n"
+	"info <imageAddr>          - display image info\n"
+	"bmp display <imageAddr> [x y] - display image at x,y\n"
 );
 
 /*
@@ -115,11 +121,17 @@ static int bmp_info(ulong addr)
  * Return:      None
  *
  */
-static int bmp_display(ulong addr)
+static int bmp_display(ulong addr, int x, int y)
 {
-	extern int lcd_display_bitmap (ulong);
+#ifdef CONFIG_LCD
+    extern int lcd_display_bitmap (ulong, int, int);
 
-	return (lcd_display_bitmap (addr));
+	return (lcd_display_bitmap (addr, x, y));
+#endif
+#ifdef CONFIG_VIDEO
+	extern int video_display_bitmap (ulong, int, int);
+	return (video_display_bitmap (addr, x, y));
+#endif
 }
 
 #endif /* (CONFIG_COMMANDS & CFG_CMD_BMP) */

cpu/mpc8260/cpu_init.c

@@ -98,7 +98,9 @@ static void config_8260_ioports (volatile immap_t * immr)
 void cpu_init_f (volatile immap_t * immr)
 {
 	DECLARE_GLOBAL_DATA_PTR;
-
+#if !defined(CONFIG_COGENT)		/* done in start.S for the cogent */
+	uint sccr;
+#endif
 	volatile memctl8260_t *memctl = &immr->im_memctl;
 	extern void m8260_cpm_reset (void);
 
@@ -131,7 +133,10 @@ void cpu_init_f (volatile immap_t * immr)
 
 #if !defined(CONFIG_COGENT)		/* done in start.S for the cogent */
 	/* System clock control register (9-8) */
-	immr->im_clkrst.car_sccr = CFG_SCCR;
+	sccr = immr->im_clkrst.car_sccr &
+		(SCCR_PCI_MODE | SCCR_PCI_MODCK | SCCR_PCIDF_MSK);
+	immr->im_clkrst.car_sccr = sccr |
+		(CFG_SCCR & ~(SCCR_PCI_MODE | SCCR_PCI_MODCK | SCCR_PCIDF_MSK) );
 #endif /* !CONFIG_COGENT */
 
 	/*

cpu/mpc8xx/lcd.c

@@ -1205,7 +1205,7 @@ static void bitmap_plot (int x, int y)
  * Display the BMP file located at address bmp_image.
  * Only uncompressed
  */
-int lcd_display_bitmap(ulong bmp_image)
+int lcd_display_bitmap(ulong bmp_image, int x, int y)
 {
 	volatile immap_t *immr = (immap_t *) CFG_IMMR;
 	volatile cpm8xx_t *cp = &(immr->im_cpm);
@@ -1277,16 +1277,14 @@ int lcd_display_bitmap(ulong bmp_image)
 	}
 
 	padded_line = (width&0x3) ? ((width&~0x3)+4) : (width);
-	if (width>panel_info.vl_col)
-		width = panel_info.vl_col;
-	if (height>panel_info.vl_row)
-		height = panel_info.vl_row;
+	if ((x + width)>panel_info.vl_col)
+		width = panel_info.vl_col - x;
+	if ((y + height)>panel_info.vl_row)
+		height = panel_info.vl_row - y;
 
 	bmap = (uchar *)bmp + le32_to_cpu (bmp->header.data_offset);
-	fb   = (uchar *)
-		(lcd_base +
-		 (((height>=panel_info.vl_row) ? panel_info.vl_row : height)-1)
-		 * lcd_line_length);
+	fb   = (uchar *) (lcd_base +
+		 (y + height - 1) * lcd_line_length + x);
 	for (i = 0; i < height; ++i) {
 		WATCHDOG_RESET();
 		for (j = 0; j < width ; j++)
@@ -1317,7 +1315,7 @@ static void *lcd_logo (void)
 	if ((s = getenv("splashimage")) != NULL) {
 		addr = simple_strtoul(s, NULL, 16);
 
-		if (lcd_display_bitmap (addr) == 0) {
+		if (lcd_display_bitmap (addr, 0, 0) == 0) {
 			return ((void *)lcd_base);
 		}
 	}

include/configs/IceCube.h

@@ -174,16 +174,16 @@
 /*
  * Flash configuration
  */
-#define CFG_FLASH_BASE		0xff000000
+#define CFG_FLASH_BASE		0xFF000000
 #define CFG_FLASH_SIZE		0x01000000
 #if !defined(CFG_LOWBOOT)
-#define CFG_ENV_ADDR		(CFG_FLASH_BASE + 0x740000 + 0x800000)
+#define CFG_ENV_ADDR		(CFG_FLASH_BASE + 0x00740000 + 0x00800000)
 #else	/* CFG_LOWBOOT */
 #if defined(CFG_LOWBOOT08)
-#define CFG_ENV_ADDR		(CFG_FLASH_BASE + 0x30000 + 0x800000)
+#define CFG_ENV_ADDR		(CFG_FLASH_BASE + 0x00040000 + 0x00800000)
 #endif
 #if defined(CFG_LOWBOOT16)
-#define CFG_ENV_ADDR		(CFG_FLASH_BASE + 0x30000)
+#define CFG_ENV_ADDR		(CFG_FLASH_BASE + 0x00040000)
 #endif
 #endif	/* CFG_LOWBOOT */
 #define CFG_MAX_FLASH_BANKS	2	/* max num of memory banks      */
@@ -207,7 +207,7 @@
 /*
  * Memory map
  */
-#define CFG_MBAR		0xf0000000
+#define CFG_MBAR		0xF0000000
 #define CFG_SDRAM_BASE		0x00000000
 #define CFG_DEFAULT_MBAR	0x80000000
 
@@ -279,10 +279,10 @@
 
 #ifdef CONFIG_MPC5200_DDR
 
-#define CFG_BOOTCS_START	0xff800000
+#define CFG_BOOTCS_START	0xFF800000
 #define CFG_BOOTCS_SIZE		0x00800000
 #define CFG_BOOTCS_CFG		0x00047801
-#define CFG_CS1_START		0xff000000
+#define CFG_CS1_START		0xFF000000
 #define CFG_CS1_SIZE		0x00800000
 #define CFG_CS1_CFG		0x00047800
 
@@ -335,7 +335,7 @@
 #define CFG_ATA_REG_OFFSET	(CFG_ATA_DATA_OFFSET)
 
 /* Offset for alternate registers	*/
-#define CFG_ATA_ALT_OFFSET	(0x005c)
+#define CFG_ATA_ALT_OFFSET	(0x005C)
 
 /* Interval between registers                                                */
 #define CFG_ATA_STRIDE          4

include/mpc8260.h

@@ -288,6 +288,10 @@
 /*-----------------------------------------------------------------------
  * SCCR - System Clock Control Register					 9-8
  */
+#define SCCR_PCI_MODE	0x00000100	/* PCI Mode	*/
+#define SCCR_PCI_MODCK	0x00000080	/* Value of PCI_MODCK pin	*/
+#define SCCR_PCIDF_MSK	0x00000078	/* PCI division factor	*/
+#define SCCR_PCIDF_SHIFT 3
 #define SCCR_CLPD	0x00000004	/* CPM Low Power Disable	*/
 #define SCCR_DFBRG_MSK	0x00000003	/* Division factor of BRGCLK Mask */
 #define SCCR_DFBRG_SHIFT 0