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@@ -566,13 +566,7 @@ fiq:
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/* */
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/* */
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/****************************************************************************/
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/****************************************************************************/
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/* Operating System Timer */
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/* Operating System Timer */
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-OSTIMER_BASE: .word 0x40a00000
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-#define OSMR3 0x0C
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-#define OSCR 0x10
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-#define OWER 0x18
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-#define OIER 0x1C
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-
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- .align 5
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+.align 5
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.globl reset_cpu
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.globl reset_cpu
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/* FIXME: this code is PXA250 specific. How is this handled on */
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/* FIXME: this code is PXA250 specific. How is this handled on */
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@@ -582,18 +576,20 @@ reset_cpu:
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/* We set OWE:WME (watchdog enable) and wait until timeout happens */
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/* We set OWE:WME (watchdog enable) and wait until timeout happens */
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- ldr r0, OSTIMER_BASE
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- ldr r1, [r0, #OWER]
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+ ldr r0, =OWER
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+ ldr r1, [r0]
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orr r1, r1, #0x0001 /* bit0: WME */
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orr r1, r1, #0x0001 /* bit0: WME */
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- str r1, [r0, #OWER]
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+ str r1, [r0]
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/* OS timer does only wrap every 1165 seconds, so we have to set */
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/* OS timer does only wrap every 1165 seconds, so we have to set */
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/* the match register as well. */
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/* the match register as well. */
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- ldr r1, [r0, #OSCR] /* read OS timer */
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+ ldr r0, =OSCR
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+ ldr r1, [r0] /* read OS timer */
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add r1, r1, #0x800 /* let OSMR3 match after */
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add r1, r1, #0x800 /* let OSMR3 match after */
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add r1, r1, #0x800 /* 4096*(1/3.6864MHz)=1ms */
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add r1, r1, #0x800 /* 4096*(1/3.6864MHz)=1ms */
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- str r1, [r0, #OSMR3]
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+ ldr r0, =OSMR3
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+ str r1, [r0]
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reset_endless:
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reset_endless:
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