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fsl_esdhc: Add function to reset the eSDHC controller

To support multiple block read command we must set abort or use auto
CMD12.  If we booted from eSDHC controller neither of these are used
and thus we need to reset the controller to allow multiple block read
to function.

Signed-off-by: Jerry Huang <Chang-Ming.Huang@freescale.com>
Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
Acked-by: Stefano Babic <sbabic@denx.de>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Jerry Huang 15 년 전
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2개의 변경된 파일18개의 추가작업 그리고 0개의 파일을 삭제
  1. 17 0
      drivers/mmc/fsl_esdhc.c
  2. 1 0
      include/fsl_esdhc.h

+ 17 - 0
drivers/mmc/fsl_esdhc.c

@@ -344,6 +344,20 @@ static int esdhc_init(struct mmc *mmc)
 	return ret;
 	return ret;
 }
 }
 
 
+static void esdhc_reset(struct fsl_esdhc *regs)
+{
+	unsigned long timeout = 100; /* wait max 100 ms */
+
+	/* reset the controller */
+	esdhc_write32(&regs->sysctl, SYSCTL_RSTA);
+
+	/* hardware clears the bit when it is done */
+	while ((esdhc_read32(&regs->sysctl) & SYSCTL_RSTA) && --timeout)
+		udelay(1000);
+	if (!timeout)
+		printf("MMC/SD: Reset never completed.\n");
+}
+
 int fsl_esdhc_initialize(bd_t *bis, struct fsl_esdhc_cfg *cfg)
 int fsl_esdhc_initialize(bd_t *bis, struct fsl_esdhc_cfg *cfg)
 {
 {
 	struct fsl_esdhc *regs;
 	struct fsl_esdhc *regs;
@@ -358,6 +372,9 @@ int fsl_esdhc_initialize(bd_t *bis, struct fsl_esdhc_cfg *cfg)
 	sprintf(mmc->name, "FSL_ESDHC");
 	sprintf(mmc->name, "FSL_ESDHC");
 	regs = (struct fsl_esdhc *)cfg->esdhc_base;
 	regs = (struct fsl_esdhc *)cfg->esdhc_base;
 
 
+	/* First reset the eSDHC controller */
+	esdhc_reset(regs);
+
 	mmc->priv = cfg;
 	mmc->priv = cfg;
 	mmc->send_cmd = esdhc_send_cmd;
 	mmc->send_cmd = esdhc_send_cmd;
 	mmc->set_ios = esdhc_set_ios;
 	mmc->set_ios = esdhc_set_ios;

+ 1 - 0
include/fsl_esdhc.h

@@ -39,6 +39,7 @@
 #define SYSCTL_PEREN		0x00000004
 #define SYSCTL_PEREN		0x00000004
 #define SYSCTL_HCKEN		0x00000002
 #define SYSCTL_HCKEN		0x00000002
 #define SYSCTL_IPGEN		0x00000001
 #define SYSCTL_IPGEN		0x00000001
+#define SYSCTL_RSTA		0x01000000
 
 
 #define IRQSTAT			0x0002e030
 #define IRQSTAT			0x0002e030
 #define IRQSTAT_DMAE		(0x10000000)
 #define IRQSTAT_DMAE		(0x10000000)