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@@ -481,6 +481,12 @@
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#define PLLMR1_266_133_66_33 (PLL_FBKDIV_8 | \
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PLL_FWDDIVA_3 | PLL_FWDDIVB_3 | \
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PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
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+#define PLLMR0_266_66_33_33 (PLL_CPUDIV_1 | PLL_PLBDIV_4 | \
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+ PLL_OPBDIV_2 | PLL_EXTBUSDIV_2 | \
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+ PLL_MALDIV_1 | PLL_PCIDIV_2)
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+#define PLLMR1_266_66_33_33 (PLL_FBKDIV_8 | \
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+ PLL_FWDDIVA_3 | PLL_FWDDIVB_3 | \
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+ PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
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/*
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* PLL Voltage Controlled Oscillator (VCO) definitions
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@@ -557,12 +563,14 @@
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#define PSR_PCI_ARBIT_EN 0x00000400
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#define PSR_NEW_MODE_EN 0x00000020 /* PPC405GPr only */
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+#ifndef CONFIG_IOP480
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/*
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* PLL Voltage Controlled Oscillator (VCO) definitions
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* Maximum and minimum values (in MHz) for correct PLL operation.
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*/
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#define VCO_MIN 400
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#define VCO_MAX 800
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+#endif /* #ifndef CONFIG_IOP480 */
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#endif /* #ifdef CONFIG_405EP */
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/******************************************************************************
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@@ -675,6 +683,7 @@ typedef struct
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unsigned long freqPCI;
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unsigned long pciIntArbEn; /* Internal PCI arbiter is enabled */
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unsigned long pciClkSync; /* PCI clock is synchronous */
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+ unsigned long freqVCOHz;
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} PPC405_SYS_INFO;
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#endif /* _ASMLANGUAGE */
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stroese