p2041rdb: fix serdes clock map

Description of SerDes clock Bank2 setting in p2041 hardware specification
is wrong, the clock map which based on it is wrong either, so fix the
serdes clock map.

wrong setting of SERDES Reference Clocks Bank2:
SW2[5:6] = ON OFF	=>100MHz for PCI mode
SW2[5:6] = OFF ON	=>125MHz for SGMII mode

right setting of SERDES Reference Clocks Bank2:
SW2[5:6] = OFF OFF	=>100MHz for PCI mode
SW2[5:6] = OFF ON	=>125MHz for SGMII mode
SW2[5:6] = ON OFF	=>156.25MHZ

Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>

board/freescale/p2041rdb/p2041rdb.c

@@ -83,10 +83,12 @@ int checkboard(void)
 	puts("SERDES Reference Clocks: ");
 	sw = in_8(&CPLD_SW(2)) >> 2;
 	for (i = 0; i < 2; i++) {
-		static const char * const freq[] = {"0", "100", "125"};
+		static const char * const freq[][3] = {{"0", "100", "125"},
+						{"100", "156.25", "125"}
+		};
 		unsigned int clock = (sw >> (2 * i)) & 3;
 
-		printf("Bank%u=%sMhz ", i+1, freq[clock]);
+		printf("Bank%u=%sMhz ", i+1, freq[i][clock]);
 	}
 	puts("\n");
 
@@ -166,22 +168,25 @@ int misc_init_r(void)
 	u32 actual[NUM_SRDS_BANKS];
 	unsigned int i;
 	u8 sw;
+	static const int freq[][3] = {
+		{0, SRDS_PLLCR0_RFCK_SEL_100, SRDS_PLLCR0_RFCK_SEL_125},
+		{SRDS_PLLCR0_RFCK_SEL_100, SRDS_PLLCR0_RFCK_SEL_156_25,
+			SRDS_PLLCR0_RFCK_SEL_125}
+	};
 
 	sw = in_8(&CPLD_SW(2)) >> 2;
 	for (i = 0; i < NUM_SRDS_BANKS; i++) {
 		unsigned int clock = (sw >> (2 * i)) & 3;
-		switch (clock) {
-		case 1:
-			actual[i] = SRDS_PLLCR0_RFCK_SEL_100;
-			break;
-		case 2:
-			actual[i] = SRDS_PLLCR0_RFCK_SEL_125;
-			break;
-		default:
+		if (clock == 0x3) {
 			printf("Warning: SDREFCLK%u switch setting of '11' is "
 			       "unsupported\n", i + 1);
 			break;
 		}
+		if (i == 0 && clock == 0)
+			puts("Warning: SDREFCLK1 switch setting of"
+				"'00' is unsupported\n");
+		else
+			actual[i] = freq[i][clock];
 	}
 
 	for (i = 0; i < NUM_SRDS_BANKS; i++) {