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@@ -405,3 +405,63 @@ void ft_board_setup(void *blob, bd_t *bd)
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fdt_fixup_board_enet(blob);
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#endif
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}
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+
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+/*
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+ * Reverse engineering switch settings.
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+ * Some bits cannot be figured out. They will be displayed as
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+ * underscore in binary format. mask[] has those bits.
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+ * Some bits are calculated differently than the actual switches
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+ * if booting with overriding by FPGA.
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+ */
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+void qixis_dump_switch(void)
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+{
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+ int i;
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+ u8 sw[9];
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+
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+ /*
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+ * Any bit with 1 means that bit cannot be reverse engineered.
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+ * It will be displayed as _ in binary format.
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+ */
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+ static const u8 mask[] = {0, 0, 0, 0, 0, 0x1, 0xdf, 0x3f, 0x1f};
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+ char buf[10];
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+ u8 brdcfg[16], dutcfg[16];
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+
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+ for (i = 0; i < 16; i++) {
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+ brdcfg[i] = qixis_read(offsetof(struct qixis, brdcfg[0]) + i);
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+ dutcfg[i] = qixis_read(offsetof(struct qixis, dutcfg[0]) + i);
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+ }
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+
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+ sw[0] = dutcfg[0];
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+ sw[1] = (dutcfg[1] << 0x07) | \
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+ ((dutcfg[12] & 0xC0) >> 1) | \
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+ ((dutcfg[11] & 0xE0) >> 3) | \
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+ ((dutcfg[6] & 0x80) >> 6) | \
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+ ((dutcfg[1] & 0x80) >> 7);
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+ sw[2] = ((brdcfg[1] & 0x0f) << 4) | \
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+ ((brdcfg[1] & 0x30) >> 2) | \
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+ ((brdcfg[1] & 0x40) >> 5) | \
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+ ((brdcfg[1] & 0x80) >> 7);
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+ sw[3] = brdcfg[2];
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+ sw[4] = ((dutcfg[2] & 0x01) << 7) | \
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+ ((dutcfg[2] & 0x06) << 4) | \
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+ ((~QIXIS_READ(present)) & 0x10) | \
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+ ((brdcfg[3] & 0x80) >> 4) | \
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+ ((brdcfg[3] & 0x01) << 2) | \
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+ ((brdcfg[6] == 0x62) ? 3 : \
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+ ((brdcfg[6] == 0x5a) ? 2 : \
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+ ((brdcfg[6] == 0x5e) ? 1 : 0)));
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+ sw[5] = ((brdcfg[0] & 0x0f) << 4) | \
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+ ((QIXIS_READ(rst_ctl) & 0x30) >> 2) | \
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+ ((brdcfg[0] & 0x40) >> 5);
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+ sw[6] = (brdcfg[11] & 0x20);
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+ sw[7] = (((~QIXIS_READ(rst_ctl)) & 0x40) << 1) | \
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+ ((brdcfg[5] & 0x10) << 2);
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+ sw[8] = ((brdcfg[12] & 0x08) << 4) | \
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+ ((brdcfg[12] & 0x03) << 5);
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+
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+ puts("DIP switch (reverse-engineering)\n");
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+ for (i = 0; i < 9; i++) {
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+ printf("SW%d = 0b%s (0x%02x)\n",
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+ i + 1, byte_to_binary_mask(sw[i], mask[i], buf), sw[i]);
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+ }
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+}
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