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@@ -30,7 +30,8 @@
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#include <dataflash.h>
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#include <dataflash.h>
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#define AT91_SPI_PCS0_DATAFLASH_CARD 0xE /* Chip Select 0: NPCS0%1110 */
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#define AT91_SPI_PCS0_DATAFLASH_CARD 0xE /* Chip Select 0: NPCS0%1110 */
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-#define AT91_SPI_PCS1_DATAFLASH_CARD 0xD /* Chip Select 0: NPCS0%1101 */
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+#define AT91_SPI_PCS1_DATAFLASH_CARD 0xD /* Chip Select 1: NPCS1%1101 */
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+#define AT91_SPI_PCS2_DATAFLASH_CARD 0xB /* Chip Select 2: NPCS2%1011 */
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#define AT91_SPI_PCS3_DATAFLASH_CARD 0x7 /* Chip Select 3: NPCS3%0111 */
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#define AT91_SPI_PCS3_DATAFLASH_CARD 0x7 /* Chip Select 3: NPCS3%0111 */
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void AT91F_SpiInit(void)
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void AT91F_SpiInit(void)
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@@ -57,7 +58,14 @@ void AT91F_SpiInit(void)
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((get_mck_clk_rate() / AT91_SPI_CLK) << 8),
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((get_mck_clk_rate() / AT91_SPI_CLK) << 8),
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AT91_BASE_SPI + AT91_SPI_CSR(1));
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AT91_BASE_SPI + AT91_SPI_CSR(1));
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#endif
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#endif
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-
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+#ifdef CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS2
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+ /* Configure CS2 */
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+ writel(AT91_SPI_NCPHA |
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+ (AT91_SPI_DLYBS & DATAFLASH_TCSS) |
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+ (AT91_SPI_DLYBCT & DATAFLASH_TCHS) |
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+ ((get_mck_clk_rate() / AT91_SPI_CLK) << 8),
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+ AT91_BASE_SPI + AT91_SPI_CSR(2));
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+#endif
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#ifdef CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS3
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#ifdef CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS3
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/* Configure CS3 */
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/* Configure CS3 */
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writel(AT91_SPI_NCPHA |
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writel(AT91_SPI_NCPHA |
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@@ -99,6 +107,12 @@ void AT91F_SpiEnable(int cs)
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writel(mode | ((AT91_SPI_PCS1_DATAFLASH_CARD<<16) & AT91_SPI_PCS),
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writel(mode | ((AT91_SPI_PCS1_DATAFLASH_CARD<<16) & AT91_SPI_PCS),
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AT91_BASE_SPI + AT91_SPI_MR);
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AT91_BASE_SPI + AT91_SPI_MR);
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break;
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break;
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+ case 2: /* Configure SPI CS2 for Serial DataFlash AT45DBxx */
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+ mode = readl(AT91_BASE_SPI + AT91_SPI_MR);
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+ mode &= 0xFFF0FFFF;
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+ writel(mode | ((AT91_SPI_PCS2_DATAFLASH_CARD<<16) & AT91_SPI_PCS),
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+ AT91_BASE_SPI + AT91_SPI_MR);
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+ break;
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case 3:
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case 3:
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mode = readl(AT91_BASE_SPI + AT91_SPI_MR);
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mode = readl(AT91_BASE_SPI + AT91_SPI_MR);
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mode &= 0xFFF0FFFF;
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mode &= 0xFFF0FFFF;
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