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@@ -603,7 +603,7 @@ static inline void enable_clock_domain(u32 *const clkctrl_reg, u32 enable_mode)
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{
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{
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clrsetbits_le32(clkctrl_reg, CD_CLKCTRL_CLKTRCTRL_MASK,
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clrsetbits_le32(clkctrl_reg, CD_CLKCTRL_CLKTRCTRL_MASK,
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enable_mode << CD_CLKCTRL_CLKTRCTRL_SHIFT);
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enable_mode << CD_CLKCTRL_CLKTRCTRL_SHIFT);
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- debug("Enable clock domain - 0x%08x\n", clkctrl_reg);
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+ debug("Enable clock domain - %p\n", clkctrl_reg);
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}
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}
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static inline void wait_for_clk_enable(u32 *clkctrl_addr)
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static inline void wait_for_clk_enable(u32 *clkctrl_addr)
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@@ -630,7 +630,7 @@ static inline void enable_clock_module(u32 *const clkctrl_addr, u32 enable_mode,
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{
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{
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clrsetbits_le32(clkctrl_addr, MODULE_CLKCTRL_MODULEMODE_MASK,
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clrsetbits_le32(clkctrl_addr, MODULE_CLKCTRL_MODULEMODE_MASK,
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enable_mode << MODULE_CLKCTRL_MODULEMODE_SHIFT);
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enable_mode << MODULE_CLKCTRL_MODULEMODE_SHIFT);
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- debug("Enable clock module - 0x%08x\n", clkctrl_addr);
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+ debug("Enable clock module - %p\n", clkctrl_addr);
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if (wait_for_enable)
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if (wait_for_enable)
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wait_for_clk_enable(clkctrl_addr);
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wait_for_clk_enable(clkctrl_addr);
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}
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}
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