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+/*
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+ * (C) Copyright 2013
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+ * Texas Instruments Incorporated.
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+ * Sricharan R <r.sricharan@ti.com>
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+ *
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+ * Derived from OMAP4 done by:
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+ * Aneesh V <aneesh@ti.com>
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+ *
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+ * TI OMAP5 AND DRA7XX common configuration settings
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+ *
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+ * See file CREDITS for list of people who contributed to this
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+ * project.
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+ *
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+ * This program is free software; you can redistribute it and/or
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+ * modify it under the terms of the GNU General Public License as
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+ * published by the Free Software Foundation; either version 2 of
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+ * the License, or (at your option) any later version.
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+ *
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+ * This program is distributed in the hope that it will be useful,
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+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
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+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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+ * GNU General Public License for more details.
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+ *
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+ * You should have received a copy of the GNU General Public License
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+ * along with this program; if not, write to the Free Software
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+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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+ * MA 02111-1307 USA
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+ */
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+
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+#ifndef __CONFIG_OMAP5_COMMON_H
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+#define __CONFIG_OMAP5_COMMON_H
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+
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+/*
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+ * High Level Configuration Options
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+ */
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+#define CONFIG_OMAP /* in a TI OMAP core */
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+#define CONFIG_OMAP54XX /* which is a 54XX */
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+#define CONFIG_OMAP_GPIO
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+
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+/* Get CPU defs */
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+#include <asm/arch/cpu.h>
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+#include <asm/arch/omap.h>
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+
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+/* Display CPU and Board Info */
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+#define CONFIG_DISPLAY_CPUINFO
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+#define CONFIG_DISPLAY_BOARDINFO
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+
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+/* Clock Defines */
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+#define V_OSCK 19200000 /* Clock output from T2 */
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+#define V_SCLK V_OSCK
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+
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+#define CONFIG_MISC_INIT_R
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+
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+#define CONFIG_OF_LIBFDT
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+#define CONFIG_CMD_BOOTZ
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+
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+#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
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+#define CONFIG_SETUP_MEMORY_TAGS
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+#define CONFIG_INITRD_TAG
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+
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+/*
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+ * Size of malloc() pool
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+ * Total Size Environment - 128k
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+ * Malloc - add 256k
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+ */
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+#define CONFIG_ENV_SIZE (128 << 10)
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+#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (256 << 10))
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+/* Vector Base */
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+#define CONFIG_SYS_CA9_VECTOR_BASE SRAM_ROM_VECT_BASE
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+
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+/*
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+ * Hardware drivers
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+ */
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+
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+/*
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+ * serial port - NS16550 compatible
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+ */
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+#define V_NS16550_CLK 48000000
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+
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+#define CONFIG_SYS_NS16550
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+#define CONFIG_SYS_NS16550_SERIAL
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+#define CONFIG_SYS_NS16550_REG_SIZE (-4)
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+#define CONFIG_SYS_NS16550_CLK V_NS16550_CLK
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+#define CONFIG_CONS_INDEX 3
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+#define CONFIG_SYS_NS16550_COM3 UART3_BASE
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+
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+#define CONFIG_BAUDRATE 115200
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+#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\
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+ 115200}
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+/* I2C */
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+#define CONFIG_HARD_I2C
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+#define CONFIG_SYS_I2C_SPEED 100000
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+#define CONFIG_SYS_I2C_SLAVE 1
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+#define CONFIG_DRIVER_OMAP34XX_I2C
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+#define CONFIG_I2C_MULTI_BUS
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+
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+
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+/* MMC */
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+#define CONFIG_GENERIC_MMC
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+#define CONFIG_MMC
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+#define CONFIG_OMAP_HSMMC
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+#define CONFIG_DOS_PARTITION
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+
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+/* MMC ENV related defines */
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+#define CONFIG_ENV_IS_IN_MMC
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+#define CONFIG_SYS_MMC_ENV_DEV 1 /* SLOT2: eMMC(1) */
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+#define CONFIG_ENV_OFFSET 0xE0000
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+#define CONFIG_CMD_SAVEENV
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+
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+#define CONFIG_SYS_CONSOLE_IS_IN_ENV
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+
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+/* Flash */
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+#define CONFIG_SYS_NO_FLASH
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+
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+/* Cache */
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+#define CONFIG_SYS_CACHELINE_SIZE 64
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+#define CONFIG_SYS_CACHELINE_SHIFT 6
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+
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+/* commands to include */
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+#include <config_cmd_default.h>
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+
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+/* Enabled commands */
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+#define CONFIG_CMD_EXT2 /* EXT2 Support */
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+#define CONFIG_CMD_FAT /* FAT support */
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+#define CONFIG_CMD_I2C /* I2C serial bus support */
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+#define CONFIG_CMD_MMC /* MMC support */
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+#define CONFIG_CMD_SAVEENV
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+
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+/* Disabled commands */
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+#undef CONFIG_CMD_NET
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+#undef CONFIG_CMD_NFS
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+#undef CONFIG_CMD_FPGA /* FPGA configuration Support */
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+#undef CONFIG_CMD_IMLS /* List all found images */
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+
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+/*
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+ * Environment setup
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+ */
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+
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+#define CONFIG_BOOTDELAY 3
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+
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+#define CONFIG_ENV_OVERWRITE
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+
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+#define CONFIG_EXTRA_ENV_SETTINGS \
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+ "loadaddr=0x82000000\0" \
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+ "console=ttyO2,115200n8\0" \
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+ "usbtty=cdc_acm\0" \
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+ "vram=16M\0" \
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+ "mmcdev=0\0" \
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+ "mmcroot=/dev/mmcblk0p2 rw\0" \
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+ "mmcrootfstype=ext3 rootwait\0" \
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+ "mmcargs=setenv bootargs console=${console} " \
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+ "vram=${vram} " \
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+ "root=${mmcroot} " \
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+ "rootfstype=${mmcrootfstype}\0" \
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+ "loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \
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+ "bootscript=echo Running bootscript from mmc${mmcdev} ...; " \
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+ "source ${loadaddr}\0" \
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+ "loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \
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+ "mmcboot=echo Booting from mmc${mmcdev} ...; " \
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+ "run mmcargs; " \
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+ "bootm ${loadaddr}\0" \
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+
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+#define CONFIG_BOOTCOMMAND \
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+ "mmc dev ${mmcdev}; if mmc rescan; then " \
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+ "if run loadbootscript; then " \
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+ "run bootscript; " \
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+ "else " \
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+ "if run loaduimage; then " \
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+ "run mmcboot; " \
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+ "fi; " \
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+ "fi; " \
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+ "fi"
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+
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+#define CONFIG_AUTO_COMPLETE 1
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+
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+/*
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+ * Miscellaneous configurable options
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+ */
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+
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+#define CONFIG_SYS_LONGHELP /* undef to save memory */
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+#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
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+#define CONFIG_SYS_CBSIZE 256
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+/* Print Buffer Size */
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+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
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+ sizeof(CONFIG_SYS_PROMPT) + 16)
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+#define CONFIG_SYS_MAXARGS 16
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+/* Boot Argument Buffer Size */
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+#define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE)
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+
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+/*
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+ * memtest setup
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+ */
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+#define CONFIG_SYS_MEMTEST_START 0x80000000
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+#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + (32 << 20))
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+
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+/* Default load address */
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+#define CONFIG_SYS_LOAD_ADDR 0x80000000
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+
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+/* Use General purpose timer 1 */
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+#define CONFIG_SYS_TIMERBASE GPT2_BASE
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+#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */
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+#define CONFIG_SYS_HZ 1000
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+
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+/*
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+ * SDRAM Memory Map
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+ * Even though we use two CS all the memory
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+ * is mapped to one contiguous block
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+ */
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+#define CONFIG_NR_DRAM_BANKS 1
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+
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+#define CONFIG_SYS_SDRAM_BASE 0x80000000
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+#define CONFIG_SYS_INIT_SP_ADDR (NON_SECURE_SRAM_END - \
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+ GENERATED_GBL_DATA_SIZE)
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+
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+#define CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS
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+
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+/* Defines for SDRAM init */
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+#ifndef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS
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+#define CONFIG_SYS_AUTOMATIC_SDRAM_DETECTION
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+#define CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS
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+#endif
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+
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+/* Defines for SPL */
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+#define CONFIG_SPL
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+#define CONFIG_SPL_FRAMEWORK
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+#define CONFIG_SPL_TEXT_BASE 0x40300350
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+#define CONFIG_SPL_MAX_SIZE 0x19000 /* 100K */
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+#define CONFIG_SPL_STACK CONFIG_SYS_INIT_SP_ADDR
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+#define CONFIG_SPL_DISPLAY_PRINT
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+
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+#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */
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+#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x200 /* 256 KB */
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+#define CONFIG_SYS_MMC_SD_FAT_BOOT_PARTITION 1
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+#define CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME "u-boot.img"
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+
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+#define CONFIG_SPL_LIBCOMMON_SUPPORT
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+#define CONFIG_SPL_LIBDISK_SUPPORT
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+#define CONFIG_SPL_I2C_SUPPORT
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+#define CONFIG_SPL_MMC_SUPPORT
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+#define CONFIG_SPL_FAT_SUPPORT
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+#define CONFIG_SPL_LIBGENERIC_SUPPORT
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+#define CONFIG_SPL_SERIAL_SUPPORT
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+#define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds"
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+
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+/*
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+ * 64 bytes before this address should be set aside for u-boot.img's
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+ * header. That is 80E7FFC0--0x80E80000 should not be used for any
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+ * other needs.
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+ */
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+#define CONFIG_SYS_TEXT_BASE 0x80E80000
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+
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+/*
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+ * BSS and malloc area 64MB into memory to allow enough
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+ * space for the kernel at the beginning of memory
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+ */
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+#define CONFIG_SPL_BSS_START_ADDR 0x84000000
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+#define CONFIG_SPL_BSS_MAX_SIZE 0x100000 /* 1 MB */
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+#define CONFIG_SYS_SPL_MALLOC_START 0x84100000
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+#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 /* 1 MB */
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+#define CONFIG_SPL_GPIO_SUPPORT
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+
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+#endif /* __CONFIG_OMAP5_COMMON_H */
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Lokesh Vutla