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@@ -29,6 +29,7 @@
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#include <asm/io.h>
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#include <asm/processor.h>
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#include <asm/fsl_law.h>
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+#include <asm/errno.h>
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#include "fsl_corenet_serdes.h"
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static u32 serdes_prtcl_map;
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@@ -91,7 +92,7 @@ int serdes_get_lane_idx(int lane)
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return lanes[lane].idx;
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}
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-int serdes_get_bank(int lane)
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+int serdes_get_bank_by_lane(int lane)
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{
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return lanes[lane].bank;
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}
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@@ -132,6 +133,41 @@ int is_serdes_configured(enum srds_prtcl device)
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return (1 << device) & serdes_prtcl_map;
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}
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+static int __serdes_get_first_lane(uint32_t prtcl, enum srds_prtcl device)
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+{
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+ int i;
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+
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+ for (i = 0; i < SRDS_MAX_LANES; i++) {
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+ if (serdes_get_prtcl(prtcl, i) == device)
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+ return i;
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+ }
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+
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+ return -ENODEV;
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+}
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+
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+/*
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+ * Returns the SERDES lane (0..SRDS_MAX_LANES-1) that routes to the given
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+ * device. This depends on the current SERDES protocol, as defined in the RCW.
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+ *
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+ * Returns a negative error code if SERDES is disabled or the given device is
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+ * not supported in the current SERDES protocol.
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+ */
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+int serdes_get_first_lane(enum srds_prtcl device)
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+{
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+ u32 prtcl;
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+ const ccsr_gur_t *gur;
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+
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+ gur = (typeof(gur))CONFIG_SYS_MPC85xx_GUTS_ADDR;
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+
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+ /* Is serdes enabled at all? */
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+ if (unlikely((in_be32(&gur->rcwsr[5]) & 0x2000) == 0))
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+ return -ENODEV;
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+
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+ prtcl = (in_be32(&gur->rcwsr[4]) & FSL_CORENET_RCWSR4_SRDS_PRTCL) >> 26;
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+
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+ return __serdes_get_first_lane(prtcl, device);
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+}
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+
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#ifndef CONFIG_SYS_DCSRBAR_PHYS
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#define CONFIG_SYS_DCSRBAR_PHYS 0x80000000 /* Must be 1GB-aligned for rev1.0 */
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#define CONFIG_SYS_DCSRBAR 0x80000000
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@@ -325,7 +361,7 @@ void fsl_serdes_init(void)
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for (lane = 0; lane < SRDS_MAX_LANES; lane++) {
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enum srds_prtcl lane_prtcl = serdes_get_prtcl(cfg, lane);
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if (serdes_lane_enabled(lane)) {
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- have_bank[serdes_get_bank(lane)] = 1;
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+ have_bank[serdes_get_bank_by_lane(lane)] = 1;
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serdes_prtcl_map |= (1 << lane_prtcl);
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}
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}
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