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@@ -90,5 +90,41 @@ int board_eth_init(bd_t *bis)
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ret |= xilinx_emaclite_initialize(bis, XILINX_EMACLITE_BASEADDR,
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ret |= xilinx_emaclite_initialize(bis, XILINX_EMACLITE_BASEADDR,
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txpp, rxpp);
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txpp, rxpp);
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#endif
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#endif
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+
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+#ifdef CONFIG_XILINX_LL_TEMAC
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+# ifdef XILINX_LLTEMAC_BASEADDR
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+# ifdef XILINX_LLTEMAC_FIFO_BASEADDR
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+ ret |= xilinx_ll_temac_eth_init(bis, XILINX_LLTEMAC_BASEADDR,
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+ XILINX_LL_TEMAC_M_FIFO, XILINX_LLTEMAC_FIFO_BASEADDR);
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+# elif XILINX_LLTEMAC_SDMA_CTRL_BASEADDR
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+# if XILINX_LLTEMAC_SDMA_USE_DCR == 1
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+ ret |= xilinx_ll_temac_eth_init(bis, XILINX_LLTEMAC_BASEADDR,
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+ XILINX_LL_TEMAC_M_SDMA_DCR,
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+ XILINX_LLTEMAC_SDMA_CTRL_BASEADDR);
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+# else
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+ ret |= xilinx_ll_temac_eth_init(bis, XILINX_LLTEMAC_BASEADDR,
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+ XILINX_LL_TEMAC_M_SDMA_PLB,
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+ XILINX_LLTEMAC_SDMA_CTRL_BASEADDR);
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+# endif
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+# endif
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+# endif
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+# ifdef XILINX_LLTEMAC_BASEADDR1
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+# ifdef XILINX_LLTEMAC_FIFO_BASEADDR1
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+ ret |= xilinx_ll_temac_eth_init(bis, XILINX_LLTEMAC_BASEADDR1,
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+ XILINX_LL_TEMAC_M_FIFO, XILINX_LLTEMAC_FIFO_BASEADDR1);
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+# elif XILINX_LLTEMAC_SDMA_CTRL_BASEADDR1
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+# if XILINX_LLTEMAC_SDMA_USE_DCR == 1
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+ ret |= xilinx_ll_temac_eth_init(bis, XILINX_LLTEMAC_BASEADDR1,
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+ XILINX_LL_TEMAC_M_SDMA_DCR,
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+ XILINX_LLTEMAC_SDMA_CTRL_BASEADDR1);
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+# else
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+ ret |= xilinx_ll_temac_eth_init(bis, XILINX_LLTEMAC_BASEADDR1,
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+ XILINX_LL_TEMAC_M_SDMA_PLB,
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+ XILINX_LLTEMAC_SDMA_CTRL_BASEADDR1);
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+# endif
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+# endif
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+# endif
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+#endif
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+
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return ret;
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return ret;
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}
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}
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