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@@ -1589,7 +1589,9 @@ typedef struct cpc_corenet {
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u32 cpcerreaddr; /* error extended address */
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u32 cpcerreaddr; /* error extended address */
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u32 cpcerraddr; /* error address */
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u32 cpcerraddr; /* error address */
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u32 cpcerrctl; /* error control */
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u32 cpcerrctl; /* error control */
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- u32 res9[105]; /* pad out to 4k */
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+ u32 res9[41]; /* pad out to 4k */
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+ u32 cpchdbcr0; /* hardware debug control register 0 */
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+ u32 res10[63]; /* pad out to 4k */
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} cpc_corenet_t;
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} cpc_corenet_t;
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#define CPC_CSR0_CE 0x80000000 /* Cache Enable */
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#define CPC_CSR0_CE 0x80000000 /* Cache Enable */
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@@ -1616,6 +1618,7 @@ typedef struct cpc_corenet {
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#define CPC_SRCR0_SRAMSZ_32_WAY 0x0000000a
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#define CPC_SRCR0_SRAMSZ_32_WAY 0x0000000a
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#define CPC_SRCR0_SRAMEN 0x00000001
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#define CPC_SRCR0_SRAMEN 0x00000001
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#define CPC_ERRDIS_TMHITDIS 0x00000080 /* multi-way hit disable */
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#define CPC_ERRDIS_TMHITDIS 0x00000080 /* multi-way hit disable */
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+#define CPC_HDBCR0_CDQ_SPEC_DIS 0x08000000
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#endif /* CONFIG_SYS_FSL_CPC */
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#endif /* CONFIG_SYS_FSL_CPC */
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/* Global Utilities Block */
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/* Global Utilities Block */
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