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@@ -204,6 +204,18 @@ _start_440:
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mfspr r1,mcsr
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mtspr mcsr,r1
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#endif
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+
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+ /*----------------------------------------------------------------*/
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+ /* CCR0 init */
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+ /*----------------------------------------------------------------*/
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+ /* Disable store gathering & broadcast, guarantee inst/data
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+ * cache block touch, force load/store alignment
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+ * (see errata 1.12: 440_33)
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+ */
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+ lis r1,0x0030 /* store gathering & broadcast disable */
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+ ori r1,r1,0x6000 /* cache touch */
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+ mtspr ccr0,r1
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+
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/*----------------------------------------------------------------*/
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/* Initialize debug */
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/*----------------------------------------------------------------*/
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@@ -225,17 +237,6 @@ _start_440:
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mtspr dbsr,r1 /* Clear all valid bits */
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skip_debug_init:
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- /*----------------------------------------------------------------*/
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- /* CCR0 init */
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- /*----------------------------------------------------------------*/
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- /* Disable store gathering & broadcast, guarantee inst/data
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- * cache block touch, force load/store alignment
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- * (see errata 1.12: 440_33)
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- */
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- lis r1,0x0030 /* store gathering & broadcast disable */
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- ori r1,r1,0x6000 /* cache touch */
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- mtspr ccr0,r1
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-
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#if defined (CONFIG_440SPE)
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/*----------------------------------------------------------------+
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| Initialize Core Configuration Reg1.
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