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@@ -219,8 +219,8 @@
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#if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
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#if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
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#define CONFIG_DDR_DATA_EYE /* use DDR2 optimization */
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#define CONFIG_DDR_DATA_EYE /* use DDR2 optimization */
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#endif
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#endif
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-#define CFG_MEM_TOP_HIDE (4 << 10) /* don't use last 4kbytes */
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- /* 440EPx errata CHIP 11 */
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+#define CONFIG_SYS_MEM_TOP_HIDE (4 << 10) /* don't use last 4kbytes */
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+ /* 440EPx errata CHIP 11 */
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/*-----------------------------------------------------------------------
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/*-----------------------------------------------------------------------
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* I2C
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* I2C
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@@ -490,8 +490,8 @@
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#endif
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#endif
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/* Memory Bank 1 (RESET) initialization */
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/* Memory Bank 1 (RESET) initialization */
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-#define CFG_EBC_PB1AP 0x7f817200 //0x03017200
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-#define CFG_EBC_PB1CR (CFG_RESET_BASE | 0x1c000)
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+#define CONFIG_SYS_EBC_PB1AP 0x7f817200 //0x03017200
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+#define CONFIG_SYS_EBC_PB1CR (CONFIG_SYS_RESET_BASE | 0x1c000)
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/* Memory Bank 4 (FPGA / 32Bit) initialization */
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/* Memory Bank 4 (FPGA / 32Bit) initialization */
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#define CONFIG_SYS_EBC_PB4AP 0x03840f40 /* BME=0,TWT=7,CSN=1,TH=7,RE=1,SOR=0,BEM=1 */
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#define CONFIG_SYS_EBC_PB4AP 0x03840f40 /* BME=0,TWT=7,CSN=1,TH=7,RE=1,SOR=0,BEM=1 */
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