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@@ -122,9 +122,9 @@ int get_clocks(void)
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u32 enc_clk;
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u32 lbiu_clk;
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u32 lclk_clk;
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- u32 ddr_clk;
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+ u32 mem_clk;
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#if defined(CONFIG_MPC8360)
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- u32 ddr_sec_clk;
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+ u32 mem_sec_clk;
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#endif
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#if defined(CONFIG_MPC8360) || defined(CONFIG_MPC832X)
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u32 qepmf;
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@@ -400,11 +400,11 @@ int get_clocks(void)
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return -12;
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}
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- ddr_clk = csb_clk *
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+ mem_clk = csb_clk *
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(1 + ((im->reset.rcwl & HRCWL_DDRCM) >> HRCWL_DDRCM_SHIFT));
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corepll = (im->reset.rcwl & HRCWL_COREPLL) >> HRCWL_COREPLL_SHIFT;
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#if defined(CONFIG_MPC8360)
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- ddr_sec_clk = csb_clk * (1 +
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+ mem_sec_clk = csb_clk * (1 +
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((im->reset.rcwl & HRCWL_LBIUCM) >> HRCWL_LBIUCM_SHIFT));
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#endif
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@@ -466,9 +466,9 @@ int get_clocks(void)
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gd->enc_clk = enc_clk;
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gd->lbiu_clk = lbiu_clk;
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gd->lclk_clk = lclk_clk;
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- gd->ddr_clk = ddr_clk;
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+ gd->mem_clk = mem_clk;
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#if defined(CONFIG_MPC8360)
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- gd->ddr_sec_clk = ddr_sec_clk;
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+ gd->mem_sec_clk = mem_sec_clk;
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#endif
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#if defined(CONFIG_MPC8360) || defined(CONFIG_MPC832X)
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gd->qe_clk = qe_clk;
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@@ -508,9 +508,9 @@ int do_clocks (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
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#endif
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printf(" Local Bus Controller:%4d MHz\n", gd->lbiu_clk / 1000000);
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printf(" Local Bus: %4d MHz\n", gd->lclk_clk / 1000000);
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- printf(" DDR: %4d MHz\n", gd->ddr_clk / 1000000);
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+ printf(" DDR: %4d MHz\n", gd->mem_clk / 1000000);
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#if defined(CONFIG_MPC8360)
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- printf(" DDR Secondary: %4d MHz\n", gd->ddr_sec_clk / 1000000);
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+ printf(" DDR Secondary: %4d MHz\n", gd->mem_sec_clk / 1000000);
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#endif
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printf(" SEC: %4d MHz\n", gd->enc_clk / 1000000);
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printf(" I2C1: %4d MHz\n", gd->i2c1_clk / 1000000);
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