Set ips dividor to 1/4 of csb clock.

Previous setting cause ips clock to be out of spec. This bug was found by John
Rigby from Freescale.

Signed-off-by: Grzegorz Bernacki <gjb@semihalf.com>

include/mpc512x.h

@@ -185,7 +185,7 @@
 
 /* SCFR1 System Clock Frequency Register 1
  */
-#define SCFR1_IPS_DIV			0x2
+#define SCFR1_IPS_DIV			0x4
 #define SCFR1_IPS_DIV_MASK		0x03800000
 #define SCFR1_IPS_DIV_SHIFT		23