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@@ -115,7 +115,6 @@
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#define USB_PHY0_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x49000)
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#define USB_PHY1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x4a000)
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#define CCM_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x44000)
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-#define ANATOP_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x48000)
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#define SNVS_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x4C000)
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#define EPIT1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x50000)
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#define EPIT2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x54000)
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