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@@ -200,9 +200,6 @@ int get_serial_clock(void)
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{
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u32 clk;
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u32 udiv;
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-#if defined(CONFIG_405CR) || defined(CONFIG_405EP) || defined(CONFIG_405GP)
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- u32 tmp;
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-#endif
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#if !defined(CONFIG_405EZ)
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u32 reg;
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#endif
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@@ -216,7 +213,6 @@ int get_serial_clock(void)
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*/
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#if defined(CONFIG_405CR) || defined(CONFIG_405GP)
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- tmp = 0;
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reg = mfdcr(CPC0_CR0) & ~CR0_MASK;
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#ifdef CONFIG_SYS_EXT_SERIAL_CLOCK
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clk = CONFIG_SYS_EXT_SERIAL_CLOCK;
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@@ -227,8 +223,11 @@ int get_serial_clock(void)
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#ifdef CONFIG_SYS_405_UART_ERRATA_59
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udiv = 31; /* Errata 59: stuck at 31 */
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#else /* CONFIG_SYS_405_UART_ERRATA_59 */
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- tmp = CONFIG_SYS_BASE_BAUD * 16;
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- udiv = (clk + tmp / 2) / tmp;
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+ {
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+ u32 tmp = CONFIG_SYS_BASE_BAUD * 16;
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+
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+ udiv = (clk + tmp / 2) / tmp;
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+ }
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if (udiv > UDIV_MAX) /* max. n bits for udiv */
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udiv = UDIV_MAX;
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#endif /* CONFIG_SYS_405_UART_ERRATA_59 */
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@@ -243,12 +242,15 @@ int get_serial_clock(void)
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#endif /* CONFIG_405CR */
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#if defined(CONFIG_405EP)
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- reg = mfdcr(CPC0_UCR) & ~(UCR0_MASK | UCR1_MASK);
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- clk = gd->cpu_clk;
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- tmp = CONFIG_SYS_BASE_BAUD * 16;
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- udiv = (clk + tmp / 2) / tmp;
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- if (udiv > UDIV_MAX) /* max. n bits for udiv */
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- udiv = UDIV_MAX;
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+ {
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+ u32 tmp = CONFIG_SYS_BASE_BAUD * 16;
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+
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+ reg = mfdcr(CPC0_UCR) & ~(UCR0_MASK | UCR1_MASK);
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+ clk = gd->cpu_clk;
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+ udiv = (clk + tmp / 2) / tmp;
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+ if (udiv > UDIV_MAX) /* max. n bits for udiv */
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+ udiv = UDIV_MAX;
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+ }
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reg |= udiv << UCR0_UDIV_POS; /* set the UART divisor */
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reg |= udiv << UCR1_UDIV_POS; /* set the UART divisor */
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mtdcr(CPC0_UCR, reg);
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