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@@ -35,6 +35,7 @@
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#include <common.h>
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#include <ioports.h>
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#include <mpc8260.h>
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+#include <asm/m8260_pci.h>
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#include <i2c.h>
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#include <spd.h>
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#include <miiphy.h>
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@@ -237,6 +238,7 @@ int board_pre_init (void)
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long int initdram (int board_type)
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{
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+ vu_long *bcsr = (vu_long *)CFG_BCSR;
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volatile immap_t *immap = (immap_t *) CFG_IMMR;
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volatile memctl8260_t *memctl = &immap->im_memctl;
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volatile uchar *ramaddr, c = 0xff;
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@@ -252,27 +254,41 @@ long int initdram (int board_type)
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immap->im_siu_conf.sc_ppc_alrh = 0x01267893;
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immap->im_siu_conf.sc_tescr1 = 0x00004000;
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+#if CONFIG_ADSTYPE == CFG_PQ2FADS
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+ if ((bcsr[3] & BCSR_PCI_MODE) == 0) { /* PCI mode selected by JP9 */
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+ immap->im_clkrst.car_sccr |= M826X_SCCR_PCI_MODE_EN;
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+ immap->im_siu_conf.sc_siumcr =
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+ (immap->im_siu_conf.sc_siumcr & ~SIUMCR_LBPC11)
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+ | SIUMCR_LBPC01;
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+ }
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+#endif /* CONFIG_ADSTYPE == CFG_PQ2FADS */
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+
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memctl->memc_mptpr = CFG_MPTPR;
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#ifdef CFG_LSDRAM_BASE
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- /* Init local bus SDRAM */
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- memctl->memc_lsrt = CFG_LSRT;
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+ /*
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+ Initialise local bus SDRAM only if the pins
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+ are configured as local bus pins and not as PCI.
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+ The configuration is determined by the HRCW.
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+ */
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+ if ((immap->im_siu_conf.sc_siumcr & SIUMCR_LBPC11) == SIUMCR_LBPC00) {
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+ memctl->memc_lsrt = CFG_LSRT;
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#if CONFIG_ADSTYPE == CFG_PQ2FADS /* CS3 */
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- memctl->memc_or3 = 0xFF803280;
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- memctl->memc_br3 = CFG_LSDRAM_BASE | 0x00001861;
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+ memctl->memc_or3 = 0xFF803280;
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+ memctl->memc_br3 = CFG_LSDRAM_BASE | 0x00001861;
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#else /* CS4 */
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- memctl->memc_or4 = 0xFFC01480;
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- memctl->memc_br4 = CFG_LSDRAM_BASE | 0x00001861;
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+ memctl->memc_or4 = 0xFFC01480;
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+ memctl->memc_br4 = CFG_LSDRAM_BASE | 0x00001861;
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#endif /* CONFIG_ADSTYPE == CFG_PQ2FADS */
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- memctl->memc_lsdmr = CFG_LSDMR | 0x28000000;
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- ramaddr = (uchar *) CFG_LSDRAM_BASE;
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- *ramaddr = c;
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- memctl->memc_lsdmr = CFG_LSDMR | 0x08000000;
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- for (i = 0; i < 8; i++) {
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+ memctl->memc_lsdmr = CFG_LSDMR | 0x28000000;
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+ ramaddr = (uchar *) CFG_LSDRAM_BASE;
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*ramaddr = c;
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+ memctl->memc_lsdmr = CFG_LSDMR | 0x08000000;
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+ for (i = 0; i < 8; i++)
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+ *ramaddr = c;
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+ memctl->memc_lsdmr = CFG_LSDMR | 0x18000000;
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+ *ramaddr = c;
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+ memctl->memc_lsdmr = CFG_LSDMR | 0x40000000;
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}
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- memctl->memc_lsdmr = CFG_LSDMR | 0x18000000;
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- *ramaddr = c;
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- memctl->memc_lsdmr = CFG_LSDMR | 0x40000000;
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#endif /* CFG_LSDRAM_BASE */
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/* Init 60x bus SDRAM */
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